Added ADR IO impedance field accessors

Change-Id: Ieb4cc85318506c17bbceaf19613c2c9e8ff6b051
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29968
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: FEIHONG YAN <fyan@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29975
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

3 files changed, 271 insertions, 73 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr.C
index 96620edbd..c7155a3b2 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr.C
@@ -43,68 +43,15 @@ using fapi2::TARGET_TYPE_SYSTEM;
 
 namespace mss
 {
-//ADR clock registers - one pair per clock leg
-const std::vector< std::pair<uint64_t, uint64_t> > adrTraits<TARGET_TYPE_MCA>::IO_TX_FET_SLICE_CLK_REG =
-{
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE3_POS },
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE2_POS },
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE6_POS },
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE7_POS },
-};
-//ADR command/address registers
-const std::vector< std::pair<uint64_t, uint64_t> > adrTraits<TARGET_TYPE_MCA>::IO_TX_FET_SLICE_CMD_ADDR_REG =
-{
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE0_POS }, //ADDR0
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE5_POS }, //ADDR1
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE2_POS }, //ADDR2
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE4_POS }, //ADDR3
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE6_POS }, //ADDR4
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE3_POS }, //ADDR5
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE1_POS }, //ADDR6
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE7_POS }, //ADDR7
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE2_POS }, //ADDR8
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE0_POS }, //ADDR9
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE5_POS }, //ADDR10
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE1_POS }, //ADDR11
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE3_POS }, //ADDR12
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE0_POS }, //ADDR13
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE1_POS }, //ADDR14/WEN
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE3_POS }, //ADDR15/CAS
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE1_POS }, //ADDR16/RAS
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE4_POS }, //ADDR17/RAS
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE7_POS }, //BA0
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE4_POS }, //BA1
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE2_POS }, //BG0
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE5_POS }, //BG1
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE0_POS }, //ACT_N
-
-};
-//ADR control registers
-const std::vector< std::pair<uint64_t, uint64_t> > adrTraits<TARGET_TYPE_MCA>::IO_TX_FET_SLICE_CNTL_REG =
-{
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE3_POS }, //CKE0
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE2_POS }, //CKE1
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE6_POS }, //CKE2
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE4_POS }, //CKE3
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE2_POS }, //ODT0
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE6_POS }, //ODT1
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE1_POS }, //ODT2
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE2_POS }, //ODT3
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE3_POS }, //PARITY
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE7_POS }, //RESET_N
-};
-//ADR chip select chip id registers
-const std::vector< std::pair<uint64_t, uint64_t> > adrTraits<TARGET_TYPE_MCA>::IO_TX_FET_SLICE_CSCID_REG =
-{
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE0_POS }, //CS0
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE0_POS }, //CS1
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE1_POS }, //CS2
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE3_POS }, //CS3
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE5_POS }, //CID0
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE0_POS }, //CID1
-    { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1, adrTraits<TARGET_TYPE_MCA>::ADR_IO_FET_SLICE_EN_LANE1_POS }, //CID2
-
-};
+// Below definitions are used to avoid linker errors
+// ADR clock registers - one pair per clock leg
+constexpr mss::pair<uint64_t, uint64_t> adrTraits<TARGET_TYPE_MCA>::IO_TX_FET_SLICE_CLK_REG[NUM_CLK_LANES];
+// ADR command/address registers
+constexpr mss::pair<uint64_t, uint64_t> adrTraits<TARGET_TYPE_MCA>::IO_TX_FET_SLICE_CMD_ADDR_REG[NUM_CMD_ADDR_LANES];
+// ADR control registers
+constexpr mss::pair<uint64_t, uint64_t> adrTraits<TARGET_TYPE_MCA>::IO_TX_FET_SLICE_CNTL_REG[NUM_CNTL_LANES];
+// ADR chip select chip id registers
+constexpr mss::pair<uint64_t, uint64_t> adrTraits<TARGET_TYPE_MCA>::IO_TX_FET_SLICE_CSCID_REG[NUM_CSCID_LANES];
 namespace adr
 {
 
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr.H
index dfb20680a..51290bf6c 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr.H
@@ -42,6 +42,7 @@
 
 #include <lib/shared/mss_const.H>
 #include <lib/utils/scom.H>
+#include <lib/utils/mss_pair.H>
 
 namespace mss
 {
@@ -75,17 +76,6 @@ class adrTraits<fapi2::TARGET_TYPE_MCA>
 {
     public:
 
-        //IO FET slice driver registers, broken up by attribute groupings:
-        //  1) CLK
-        //  2) ADR
-        //  3) CNTL
-        //  4) CS/CID
-        // The vector contains a pair < register, bit position >
-        static const std::vector< std::pair<uint64_t, uint64_t> > IO_TX_FET_SLICE_CLK_REG;
-        static const std::vector< std::pair<uint64_t, uint64_t> > IO_TX_FET_SLICE_CMD_ADDR_REG;
-        static const std::vector< std::pair<uint64_t, uint64_t> > IO_TX_FET_SLICE_CNTL_REG;
-        static const std::vector< std::pair<uint64_t, uint64_t> > IO_TX_FET_SLICE_CSCID_REG;
-
         enum
         {
             // Each register has two fields. One for the even lane and one for the odd lane.
@@ -120,6 +110,70 @@ class adrTraits<fapi2::TARGET_TYPE_MCA>
             NUM_CNTL_LANES = 10,
             NUM_CSCID_LANES = 7,
         };
+
+        //IO FET slice driver registers, broken up by attribute groupings:
+        //  1) CLK
+        //  2) ADR
+        //  3) CNTL
+        //  4) CS/CID
+        // The vector contains a pair < register, bit position >
+        static constexpr mss::pair<uint64_t, uint64_t> IO_TX_FET_SLICE_CLK_REG[NUM_CLK_LANES]  =
+        {
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1, ADR_IO_FET_SLICE_EN_LANE3_POS }, //CLK00 P
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1, ADR_IO_FET_SLICE_EN_LANE2_POS }, //CLK00 N
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1, ADR_IO_FET_SLICE_EN_LANE7_POS }, //CLK01 P
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1, ADR_IO_FET_SLICE_EN_LANE6_POS }, //CLK01 N
+        };
+        static constexpr mss::pair<uint64_t, uint64_t> IO_TX_FET_SLICE_CMD_ADDR_REG[NUM_CMD_ADDR_LANES]  =
+        {
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0, ADR_IO_FET_SLICE_EN_LANE0_POS }, //ADDR0
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2, ADR_IO_FET_SLICE_EN_LANE5_POS }, //ADDR1
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1, ADR_IO_FET_SLICE_EN_LANE2_POS }, //ADDR2
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2, ADR_IO_FET_SLICE_EN_LANE4_POS }, //ADDR3
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2, ADR_IO_FET_SLICE_EN_LANE6_POS }, //ADDR4
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2, ADR_IO_FET_SLICE_EN_LANE3_POS }, //ADDR5
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2, ADR_IO_FET_SLICE_EN_LANE1_POS }, //ADDR6
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2, ADR_IO_FET_SLICE_EN_LANE7_POS }, //ADDR7
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2, ADR_IO_FET_SLICE_EN_LANE2_POS }, //ADDR8
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2, ADR_IO_FET_SLICE_EN_LANE0_POS }, //ADDR9
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0, ADR_IO_FET_SLICE_EN_LANE5_POS }, //ADDR10
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3, ADR_IO_FET_SLICE_EN_LANE1_POS }, //ADDR11
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2, ADR_IO_FET_SLICE_EN_LANE3_POS }, //ADDR12
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1, ADR_IO_FET_SLICE_EN_LANE0_POS }, //ADDR13
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0, ADR_IO_FET_SLICE_EN_LANE1_POS }, //ADDR14/WEN
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0, ADR_IO_FET_SLICE_EN_LANE3_POS }, //ADDR15/CAS
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2, ADR_IO_FET_SLICE_EN_LANE1_POS }, //ADDR16/RAS
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1, ADR_IO_FET_SLICE_EN_LANE4_POS }, //ADDR17/RAS
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0, ADR_IO_FET_SLICE_EN_LANE7_POS }, //BA0
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0, ADR_IO_FET_SLICE_EN_LANE4_POS }, //BA1
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3, ADR_IO_FET_SLICE_EN_LANE2_POS }, //BG0
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3, ADR_IO_FET_SLICE_EN_LANE5_POS }, //BG1
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3, ADR_IO_FET_SLICE_EN_LANE0_POS }, //ACT_N
+
+        };
+        static constexpr mss::pair<uint64_t, uint64_t> IO_TX_FET_SLICE_CNTL_REG[NUM_CNTL_LANES] =
+        {
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3, ADR_IO_FET_SLICE_EN_LANE3_POS }, //CKE0
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2, ADR_IO_FET_SLICE_EN_LANE2_POS }, //CKE1
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3, ADR_IO_FET_SLICE_EN_LANE6_POS }, //CKE2
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3, ADR_IO_FET_SLICE_EN_LANE4_POS }, //CKE3
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0, ADR_IO_FET_SLICE_EN_LANE2_POS }, //ODT0
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0, ADR_IO_FET_SLICE_EN_LANE6_POS }, //ODT1
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0, ADR_IO_FET_SLICE_EN_LANE1_POS }, //ODT2
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0, ADR_IO_FET_SLICE_EN_LANE2_POS }, //ODT3
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1, ADR_IO_FET_SLICE_EN_LANE3_POS }, //PARITY
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3, ADR_IO_FET_SLICE_EN_LANE7_POS }, //RESET_N
+        };
+        static constexpr mss::pair<uint64_t, uint64_t> IO_TX_FET_SLICE_CSCID_REG[NUM_CSCID_LANES] =
+        {
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0, ADR_IO_FET_SLICE_EN_LANE0_POS }, //CS0
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1, ADR_IO_FET_SLICE_EN_LANE1_POS }, //CS1
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2, ADR_IO_FET_SLICE_EN_LANE0_POS }, //CS2
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1, ADR_IO_FET_SLICE_EN_LANE1_POS }, //CS3
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0, ADR_IO_FET_SLICE_EN_LANE3_POS }, //CID0
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1, ADR_IO_FET_SLICE_EN_LANE5_POS }, //CID1
+            { MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1, ADR_IO_FET_SLICE_EN_LANE0_POS }, //CID2
+        };
 };
 
 ///
@@ -147,6 +201,8 @@ namespace adr
 ///
 fapi2::ReturnCode reset_delay( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target );
 
+//TODO RTC:161327 Change API to use or to have a function parameter version for ADR IO IMP
+
 ///
 /// @brief sets up the clock driver impedances
 /// @tparam T the type of the target in question
@@ -367,6 +423,153 @@ fapi_try_exit:
     return fapi2::current_err;
 }
 
+//////////////////////////////////////////
+// ADR impedance field access functions //
+//////////////////////////////////////////
+///
+/// @brief Writes the chip select's/chip id's output impedance field
+/// @tparam I Clock lane instance
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to adrTraits<T>
+/// @param[in,out] io_data register data to modify
+/// @param[in] i_field - field data to change
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< uint64_t I, fapi2::TargetType T, typename TT = adrTraits<T> >
+inline void set_imp_cscid( fapi2::buffer<uint64_t>& io_data,
+                           const bool i_field )
+{
+    static_assert( I < TT::NUM_CSCID_LANES, "lane instance out of range");
+
+    // modifies the data
+    io_data.writeBit<TT::IO_TX_FET_SLICE_CSCID_REG[I].second>(i_field);
+}
+
+///
+/// @brief Reads the chip select's/chip id's output impedance field
+/// @tparam I Clock lane instance
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to adrTraits<T>
+/// @param[in] i_data the field data
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< uint64_t I, fapi2::TargetType T, typename TT = adrTraits<T> >
+inline const bool get_imp_cscid( const fapi2::buffer<uint64_t>& i_data )
+{
+    static_assert( I < TT::NUM_CSCID_LANES, "lane instance out of range");
+
+    // sends the output data
+    return i_data.getBit<TT::IO_TX_FET_SLICE_CSCID_REG[I].second>();
+}
+
+///
+/// @brief Writes the clocks's output impedance field
+/// @tparam I Clock lane instance
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to adrTraits<T>
+/// @param[in,out] io_data register data to modify
+/// @param[in] i_field - field data to change
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< uint64_t I, fapi2::TargetType T, typename TT = adrTraits<T> >
+inline void set_imp_clk( fapi2::buffer<uint64_t>& io_data,
+                         const bool i_field )
+{
+    static_assert( I < TT::NUM_CLK_LANES, "lane instance out of range");
+
+    // modifies the data
+    io_data.writeBit<TT::IO_TX_FET_SLICE_CLK_REG[I].second>(i_field);
+}
+
+///
+/// @brief Reads the clock's output impedance field
+/// @tparam I Clock lane instance
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to adrTraits<T>
+/// @param[in] i_data the field data
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< uint64_t I, fapi2::TargetType T, typename TT = adrTraits<T> >
+inline fapi2::ReturnCode get_imp_clk( const fapi2::buffer<uint64_t>& i_data )
+{
+    static_assert( I < TT::NUM_CLK_LANES, "lane instance out of range");
+
+    // sends the output data
+    return i_data.getBit<TT::IO_TX_FET_SLICE_CLK_REG[I].second>();
+}
+
+///
+/// @brief Writes the command/address's output impedance field
+/// @tparam I Clock lane instance
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to adrTraits<T>
+/// @param[in,out] io_data register data to modify
+/// @param[in] i_field - field data to change
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< uint64_t I, fapi2::TargetType T, typename TT = adrTraits<T> >
+inline void set_imp_cmd_addr( fapi2::buffer<uint64_t>& io_data,
+                              const bool i_field )
+{
+    static_assert( I < TT::NUM_CMD_ADDR_LANES, "lane instance out of range");
+
+    // modifies the data
+    io_data.writeBit<TT::IO_TX_FET_SLICE_CMD_ADDR_REG[I].second>(i_field);
+}
+
+///
+/// @brief Reads the command/addresses's output impedance field
+/// @tparam I Clock lane instance
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to adrTraits<T>
+/// @param[in] i_data the field data
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< uint64_t I, fapi2::TargetType T, typename TT = adrTraits<T> >
+inline const bool get_imp_cmd_addr( const fapi2::buffer<uint64_t>& i_data )
+{
+    static_assert( I < TT::NUM_CMD_ADDR_LANES, "lane instance out of range");
+
+    // sends the output data
+    return i_data.getBit<TT::IO_TX_FET_SLICE_CMD_ADDR_REG[I].second>();
+}
+
+///
+/// @brief Writes the control signal's output impedance field
+/// @tparam I Clock lane instance
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to adrTraits<T>
+/// @param[in,out] io_data register data to modify
+/// @param[in] i_field - field data to change
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< uint64_t I, fapi2::TargetType T, typename TT = adrTraits<T> >
+inline void set_imp_cntl( fapi2::buffer<uint64_t>& io_data,
+                          const bool i_field )
+{
+    static_assert( I < TT::NUM_CNTL_LANES, "lane instance out of range");
+
+    // modifies the data
+    io_data.writeBit<TT::IO_TX_FET_SLICE_CNTL_REG[I].second>(i_field);
+}
+
+///
+/// @brief Reads the control signal's output impedance field
+/// @tparam I Clock lane instance
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to adrTraits<T>
+/// @param[in] i_data the field data
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< uint64_t I, fapi2::TargetType T, typename TT = adrTraits<T> >
+inline const bool get_imp_cntl( const fapi2::buffer<uint64_t>& i_data )
+{
+    static_assert( I < TT::NUM_CNTL_LANES, "lane instance out of range");
+
+    // sends the output data
+    return i_data.getBit<TT::IO_TX_FET_SLICE_CNTL_REG[I].second>();
+}
+
 } // close namespace adr
 
 } // close namespace mss
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/mss_pair.H b/src/import/chips/p9/procedures/hwp/memory/lib/utils/mss_pair.H
index c9be386e8..305ec3489 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/mss_pair.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/mss_pair.H
@@ -33,3 +33,51 @@
 // *HWP Level: 2
 // *HWP Consumed by: HB:FSP
 
+
+#ifndef _MSS_PAIR_CONST_H_
+#define _MSS_PAIR_CONST_H_
+
+#include <fapi2.H>
+#include <lib/utils/find.H>
+#include <lib/utils/c_str.H>
+
+namespace mss
+{
+
+///
+/// @brief a version of std::pair that has a constexpr constructor
+/// allows for MUCH cleaner code and code that can be run at compile time
+/// @tparam T1 - type of first
+/// @tparam T2 - type of second
+///
+template <typename T1, typename T2>
+struct pair
+{
+    // forces the user to initialize the values
+    pair() = delete;
+
+    // disables the copy constructor
+    pair( const pair<T1, T2>& i_rhs) = delete;
+
+    ///
+    /// @brief default destructor
+    ///
+    ~pair() = default;
+
+    ///
+    /// @brief constexpr constructor
+    /// @param[in] i_first - input to the first internal variable
+    /// @param[in] i_second - input to the second internal variable
+    ///
+    constexpr pair(const T1& i_first, const T2& i_second) :
+        first(i_first),
+        second(i_second)
+    {}
+
+    // not using iv_ to keep this as close as possible to pair
+    T1 first;
+    T2 second;
+};
+
+}
+#endif