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| author | Prasad Bg Ranganath <prasadbgr@in.ibm.com> | 2017-11-15 02:31:34 -0600 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2017-11-30 19:30:26 -0500 |
| commit | 4319e2a93d9aa63a5463fc4c586e605c84f3ebfa (patch) | |
| tree | 8f301660fdd5b8337cf7def14b43f22bde3dab11 /src/import/chips/p9/procedures/hwp | |
| parent | 1c06b1a80e5ec74725d65ba63a5b1cdce7e1ab52 (diff) | |
| download | talos-hostboot-4319e2a93d9aa63a5463fc4c586e605c84f3ebfa.tar.gz talos-hostboot-4319e2a93d9aa63a5463fc4c586e605c84f3ebfa.zip | |
p9_pm_pstate_gpe_init: setup Fsafe in all configured QPPMs
Key_Cronus_Test=PM_REGRESS
RTC:180835
CQ:SW409454
Change-Id: I35d437ad7aee0c99be6281e1b745a195e2e6479f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49720
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49723
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/pm/p9_pm_pstate_gpe_init.C | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_pstate_gpe_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_pstate_gpe_init.C index 14e778ae0..e82e1034e 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_pstate_gpe_init.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_pstate_gpe_init.C @@ -40,6 +40,8 @@ #include <p9_pm_hcd_flags.h> #include <p9_ppe_defs.H> #include <p9_ppe_utils.H> +#include <p9_quad_scom_addresses.H> +#include <p9_quad_scom_addresses_fld.H> #include <vector> // ----------------------------------------------------------------------------- @@ -242,6 +244,32 @@ fapi2::ReturnCode pstate_gpe_init( "Pstate GPE Protocol Auto Start timeout"); } } + + //Update QPPM_QPMMR_FSAFE + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; + auto l_eqChiplets = i_target.getChildren<fapi2::TARGET_TYPE_EQ> + (fapi2::TARGET_STATE_FUNCTIONAL); + fapi2::ATTR_SAFE_MODE_FREQUENCY_MHZ_Type l_attr_safe_mode_freq_mhz; + fapi2::ATTR_FREQ_PROC_REFCLOCK_KHZ_Type l_ref_clock_freq_khz; + fapi2::ATTR_PROC_DPLL_DIVIDER_Type l_proc_dpll_divider; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SAFE_MODE_FREQUENCY_MHZ, i_target, l_attr_safe_mode_freq_mhz)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FREQ_PROC_REFCLOCK_KHZ, FAPI_SYSTEM, l_ref_clock_freq_khz)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_DPLL_DIVIDER, i_target, l_proc_dpll_divider)); + // Convert frequency value to a format that needs to be written to the + // register + uint32_t l_safe_mode_freq = ((l_attr_safe_mode_freq_mhz * 1000) * l_proc_dpll_divider) / + l_ref_clock_freq_khz; + + for (auto l_eq_chplt : l_eqChiplets) + { + FAPI_TRY(getScom(l_eq_chplt, EQ_QPPM_QPMMR, l_data64)); + //FSAFE + l_data64.insertFromRight<EQ_QPPM_QPMMR_FSAFE, + EQ_QPPM_QPMMR_FSAFE_LEN>(l_safe_mode_freq); + + FAPI_TRY(fapi2::putScom(l_eq_chplt, EQ_QPPM_QPMMR, l_data64), + "ERROR:Failed to write for EQ_QPPM_QPMMR"); + } } else { |
