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authorRicardo Mata <ricmata@us.ibm.com>2017-01-23 21:28:12 -0600
committerDaniel M. Crowell <dcrowell@us.ibm.com>2017-02-10 21:57:57 -0500
commit23f9d13c49a4ed249fd0980643d440d99f8cfb5c (patch)
tree2380c1d252f9584a265a98bb2000e3eddbeee0d5 /src/import/chips/p9/procedures/hwp
parent68134ad6a5854365740bb0fd39b8b822d6eddae4 (diff)
downloadtalos-hostboot-23f9d13c49a4ed249fd0980643d440d99f8cfb5c.tar.gz
talos-hostboot-23f9d13c49a4ed249fd0980643d440d99f8cfb5c.zip
p9_pcie_scominit PEC0 swap bit position fixed
set DD1.0x workaround attributes explicitly in p9_getecid Change-Id: I4a30ccd741da885a1c36160a0e73b38898105b18 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35296 Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35321 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp')
-rw-r--r--src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.H2
-rw-r--r--src/import/chips/p9/procedures/hwp/perv/p9_getecid.C37
2 files changed, 22 insertions, 17 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.H b/src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.H
index a750703ce..03ecc363c 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.H
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.H
@@ -96,7 +96,7 @@ const uint8_t PEC2_IOP_CONFIG_START_BIT = 10;
const uint8_t PEC0_IOP_BIT_COUNT = 1;
const uint8_t PEC1_IOP_BIT_COUNT = 2;
const uint8_t PEC2_IOP_BIT_COUNT = 3;
-const uint8_t PEC0_IOP_SWAP_START_BIT = 11;
+const uint8_t PEC0_IOP_SWAP_START_BIT = 12;
const uint8_t PEC1_IOP_SWAP_START_BIT = 12;
const uint8_t PEC2_IOP_SWAP_START_BIT = 7;
const uint8_t PEC0_IOP_IOVALID_ENABLE_START_BIT = 4;
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_getecid.C b/src/import/chips/p9/procedures/hwp/perv/p9_getecid.C
index 753d323d6..8dc15b71c 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_getecid.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_getecid.C
@@ -60,17 +60,20 @@ static fapi2::ReturnCode setup_pcie_work_around_attributes(
l_ec_feature_pcie_lock_phase_rotator),
"Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_PCIE_LOCK_PHASE_ROTATOR)");
+ uint8_t l_value = 0;
+
if (l_ec_feature_pcie_lock_phase_rotator && (l_version < ddLevelPciePart))
{
- FAPI_DBG("seeing version 1.00 (0x%x) setting attributes", l_version);
- uint8_t l_value = 1;
-
- for (auto& l_pec_trgt : i_target.getChildren<fapi2::TARGET_TYPE_PEC>(fapi2::TARGET_STATE_FUNCTIONAL))
- {
- FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_PCIE_PCS_RX_ROT_EXTEL, l_pec_trgt, l_value),
- "Error from FAPI_ATTR_SET (ATTR_PROC_PCIE_PCS_RX_ROT_EXTEL)");
- }
+ FAPI_DBG("seeing version 1.00 (0x%x) setting ATTR_PROC_PCIE_PCS_RX_ROT_EXTEL", l_version);
+ l_value = 1;
}
+
+ for (auto& l_pec_trgt : i_target.getChildren<fapi2::TARGET_TYPE_PEC>(fapi2::TARGET_STATE_FUNCTIONAL))
+ {
+ FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_PCIE_PCS_RX_ROT_EXTEL, l_pec_trgt, l_value),
+ "Error from FAPI_ATTR_SET (ATTR_PROC_PCIE_PCS_RX_ROT_EXTEL)");
+ }
+
}
{
// Workarounds for DD1.01/DD1.02 modules
@@ -78,16 +81,18 @@ static fapi2::ReturnCode setup_pcie_work_around_attributes(
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_PCIE_DISABLE_FDDC, i_target, l_ec_feature_pcie_disable_fddc),
"Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_PCIE_DISABLE_FDDC)");
+ uint8_t l_value = 1;
+
if (l_ec_feature_pcie_disable_fddc && (l_version >= ddLevelPciePart))
{
- FAPI_DBG("seeing version >= 1.01 (0x%x) setting attributes", l_version);
- uint8_t l_value = 0;
-
- for (auto& l_pec_trgt : i_target.getChildren<fapi2::TARGET_TYPE_PEC>(fapi2::TARGET_STATE_FUNCTIONAL))
- {
- FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_PCIE_PCS_RX_DFE_FDDC, l_pec_trgt, l_value),
- "Error from FAPI_ATTR_SET (ATTR_PROC_PCIE_PCS_RX_DFE_FDDC)");
- }
+ FAPI_DBG("seeing version >= 1.01 (0x%x) clearing ATTR_PROC_PCIE_PCS_RX_DFE_FDDC", l_version);
+ l_value = 0;
+ }
+
+ for (auto& l_pec_trgt : i_target.getChildren<fapi2::TARGET_TYPE_PEC>(fapi2::TARGET_STATE_FUNCTIONAL))
+ {
+ FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_PCIE_PCS_RX_DFE_FDDC, l_pec_trgt, l_value),
+ "Error from FAPI_ATTR_SET (ATTR_PROC_PCIE_PCS_RX_DFE_FDDC)");
}
}
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