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| author | Prem Shanker Jha <premjha2@in.ibm.com> | 2017-01-10 05:35:49 -0600 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2017-01-16 09:17:13 -0500 |
| commit | d02ef46e2d00833f22e6f7953485b2dd63a31a08 (patch) | |
| tree | 55979979baf717ee837186d6efb81727c576a18e /src/import/chips/p9/procedures/hwp/pm | |
| parent | a1cab72496e8af3958c0dfc2690afe80e2728a24 (diff) | |
| download | talos-hostboot-d02ef46e2d00833f22e6f7953485b2dd63a31a08.tar.gz talos-hostboot-d02ef46e2d00833f22e6f7953485b2dd63a31a08.zip | |
PM: Fixed placement issue associated with core repair rings in HOMER.
Commit fixes issue reported with ec_repr ring. Ring payload was
starting from the incorrect location. As a result, repair ring for
even core in a given EX would have header bytes overwritten. Problem
impacts RS4v2 and RSv3 alike.
It did not break putring because
- Ring offset in the index was still correct
- Puting doesn't uses the header bytes which were overwritten.
Change-Id: I4a8941927242d5ed391031740142f9c1039bb585
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34654
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: ASHISH A. MORE <ashish.more@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34656
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/pm')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C index a39941612..1bf79981b 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C @@ -615,7 +615,7 @@ extern "C" sgpeFlag |= SGPE_STOP_11_TO_8_BIT_POS; } - FAPI_DBG("STOP_11_to_8 : %s", attrVal ? "TRUE" : "FALSE" ); + FAPI_DBG("STOP_11_to_8 : %s", attrVal ? "TRUE" : "FALSE" ); //Handling SGPE specific flag FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_ADDR_BAR_MODE, @@ -629,7 +629,7 @@ extern "C" sgpeFlag |= SGPE_PROC_FAB_ADDR_BAR_MODE_POS; } - FAPI_DBG("SMALL_SYSTEM : %s", attrVal ? "TRUE" : "FALSE" ); + FAPI_DBG("SMALL_SYSTEM : %s", attrVal ? "TRUE" : "FALSE" ); //Updating flag field in CME/SGPE Image header pCmeHdr->g_cme_mode_flags = SWIZZLE_4_BYTE(cmeFlag); pSgpeHdr->g_sgpe_reserve_flags = SWIZZLE_4_BYTE(sgpeFlag); @@ -1575,8 +1575,11 @@ extern "C" maxCoreSpecRingLength = ringLength > maxCoreSpecRingLength ? ringLength : maxCoreSpecRingLength; } - maxCoreSpecRingLength += sizeof(CoreSpecRingList_t); - ROUND_OFF_32B(maxCoreSpecRingLength); + if( maxCoreSpecRingLength > 0 ) + { + maxCoreSpecRingLength += sizeof(CoreSpecRingList_t); + ROUND_OFF_32B(maxCoreSpecRingLength); + } FAPI_DBG("Max Instance Spec Ring 0x%08X", maxCoreSpecRingLength); // Let us copy the rings now. @@ -1588,7 +1591,7 @@ extern "C" for( uint32_t exId = 0; exId < MAX_CME_PER_CHIP; exId++ ) { pRingStart = (uint8_t*)&i_pHomer->cpmrRegion.cmeSramRegion[io_ringLength + ( exId * maxCoreSpecRingLength ) ]; - pRingPayload = &i_pHomer->cpmrRegion.cmeSramRegion[ io_ringLength + ( exId * maxCoreSpecRingLength ) ]; + pRingPayload = pRingStart + sizeof(CoreSpecRingList_t); pScanRingIndex = (uint16_t*)pRingStart; if( !i_chipState.isExFunctional( exId ) ) |
