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| author | Prem Shanker Jha <premjha2@in.ibm.com> | 2018-07-11 04:33:28 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-08-20 10:38:20 -0500 |
| commit | a30c34acdf4cb131711c9c9df539e38703c84217 (patch) | |
| tree | 8c45f6e5f116416a3a2df75f4daa6a173e136b62 /src/import/chips/p9/procedures/hwp/pm | |
| parent | 9a96890811e788f6297adb37762bfea72448cb4f (diff) | |
| download | talos-hostboot-a30c34acdf4cb131711c9c9df539e38703c84217.tar.gz talos-hostboot-a30c34acdf4cb131711c9c9df539e38703c84217.zip | |
SCOM Restore: Increased max eq scom restores entries supported to 255.
Commit increases max eq scom restore entries supported from 63
to 255. It updates a field in QPMR header which is read by STOP API
and SGPE Hcode. This enables a flexible way to change SCOM
restore entries.
Key_Cronus_Test=PM_REGRESS
HW-Image-Prereq: Ie13a5110384e4161615167b238aecd4e2e0b9902
Change-Id: I036691f2fa152b1f0597e133b37b1795837d6e45
CQ: SW435708
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/62222
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/62242
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/pm')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C index b92d67fdb..fa0340fac 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C @@ -136,6 +136,8 @@ enum L2_EPS_DIVIDER = 1, MAX_HOMER_HEADER = 6, MAX_PM_REGION_HEADER = 3, + MAX_EQ_SCOM_RESTORES = 255, + SGPE_IMGAE_VERSION = 0x003, //Keeping in HWP to avoid hcode-HWP coreq }; /** @@ -1314,7 +1316,8 @@ void updateQpmrHeader( Homerlayout_t* i_pChipHomer, QpmrHeaderLayout_t& io_qpmrH SWIZZLE_4_BYTE(io_qpmrHdr.quadCommonRingLength) + SWIZZLE_4_BYTE(io_qpmrHdr.quadSpecRingLength); - io_qpmrHdr.maxQuadScomRestoreEntry = SWIZZLE_4_BYTE(QUAD_SCOM_RESTORE_REGS_PER_QUAD - 1); + io_qpmrHdr.maxQuadScomRestoreEntry = SWIZZLE_4_BYTE(MAX_EQ_SCOM_RESTORES); //Keeping it all in HWP to avoid hcode-HWP coreq + io_qpmrHdr.buildVersion = SWIZZLE_4_BYTE(SGPE_IMGAE_VERSION); io_qpmrHdr.sgpeSramImageSize = SWIZZLE_4_BYTE(io_qpmrHdr.sgpeSramImageSize); memcpy( pQpmrHdr, &io_qpmrHdr, sizeof( QpmrHeaderLayout_t ) ); |
