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| author | Greg Still <stillgs@us.ibm.com> | 2019-02-15 17:03:22 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2019-02-22 12:57:42 -0600 |
| commit | 475664f1fa358f56e44aa128accba27a4cdc9aa4 (patch) | |
| tree | dd0883c27aac777f4e9a8891c68cab771cac2a83 /src/import/chips/p9/procedures/hwp/pm | |
| parent | 688a9733e614a8cb04224f5c7e33da4170f87f51 (diff) | |
| download | talos-hostboot-475664f1fa358f56e44aa128accba27a4cdc9aa4.tar.gz talos-hostboot-475664f1fa358f56e44aa128accba27a4cdc9aa4.zip | |
PM: fix cable pull issue in clearing clock sync upon PM Complex Reset
- Don't clear CACCR[15] (clock sync enable); allow it to be fully managed
by STOP entry/exit in CME Hcode.
Key_Cronus_Test=PM_REGRESS
Change-Id: I92cc74043b8aefd7351ff765083de703675b8a39
CQ: SW453649
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71990
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: RAHUL BATRA <rbatra@us.ibm.com>
Dev-Ready: Michael S. Floyd <mfloyd@us.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71991
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/pm')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C index 47f6f561d..77cd232e8 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -585,7 +585,7 @@ fapi2::ReturnCode pm_corequad_reset( uint16_t l_qaccr_value = 0; uint16_t l_caccr_value = 0; l_address = EQ_QPPM_QACCR; - uint8_t l_caccr_bit_13_14_15_value = 0; + uint8_t l_caccr_bit_13_14_value = 0; FAPI_TRY(fapi2::getScom(l_quad_chplt, l_address, l_quad_data64), "ERROR: Failed to read EQ_QPPM_QACCR"); @@ -616,7 +616,7 @@ fapi2::ReturnCode pm_corequad_reset( FAPI_TRY(fapi2::getScom(l_core_chplt, l_address, l_core_data64), "ERROR: Failed to read C_CPPM_CACCR"); - //extract 0:11 bits data + //extract 0:11 (SB_STRENGH, PULSE_MODE, SW VALUE) l_core_data64.extract<C_CPPM_CACCR_CLK_SB_STRENGTH, C_CPPM_CACCR_CLK_SW_SPARE>(l_caccr_value); @@ -635,15 +635,15 @@ fapi2::ReturnCode pm_corequad_reset( } else { - //extract 13:14:15 bits + //extract 13:14 (SB OVERRIDE, SW OVERRIDE) l_core_data64. - extractToRight<C_CPPM_CACCR_QUAD_CLK_SB_OVERRIDE, 3>(l_caccr_bit_13_14_15_value); + extractToRight<C_CPPM_CACCR_QUAD_CLK_SB_OVERRIDE, 2>(l_caccr_bit_13_14_value); - if (l_caccr_bit_13_14_15_value) + if (l_caccr_bit_13_14_value) { //Clear override bits - l_core_data64.insert<C_CPPM_CACCR_QUAD_CLK_SB_OVERRIDE, 3>(0); - FAPI_TRY(fapi2::putScom(l_core_chplt, l_address, l_core_data64), + l_core_data64.flush<0>().setBit<13, 2>(); + FAPI_TRY(fapi2::putScom(l_core_chplt, C_CPPM_CACCR_CLEAR, l_core_data64), "ERROR: Failed to write C_CPPM_CACCR"); } @@ -835,9 +835,9 @@ fapi2::ReturnCode pm_disable_resclk( } // By default clear override bits before QACCR is updated - //bit 13:14:15 - l_core_data64.insert<C_CPPM_CACCR_QUAD_CLK_SB_OVERRIDE, 3>(0); - FAPI_TRY(fapi2::putScom(l_core_chplt, l_address, l_core_data64), + // bit 13:14 + l_core_data64.flush<0>().setBit<13, 2>(); + FAPI_TRY(fapi2::putScom(l_core_chplt, C_CPPM_CACCR_CLEAR, l_core_data64), "ERROR: Failed to write C_CPPM_CACCR"); } //end of core list |
