create attribute to reflect DPLL input frequency

HWP code currently references the CP reference clock frequency as the
basis for DPLL programming.

This commit creates a new attribute to reflect the DPLL input clock
frequency, and sets its default value to 133 MHz, which is correct
for all current systems, regardless of the CP reference clock
frequency -- all p9n, p9c system configurations use a 133 MHz CP reference clock
input, while p9a systems will use 100 MHz.

Change-Id: I01685cb0346cc5b61edd8ff739717875fcf0f3a0
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78220
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78224
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

5 files changed, 16 insertions, 16 deletions

diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C
index 77cd232e8..db22f670e 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C
@@ -684,14 +684,14 @@ fapi2::ReturnCode pm_disable_resclk(
     uint16_t l_quad_table_value;
     uint8_t l_caccr_bit_13_14_value = 0;
 
-    uint32_t attr_freq_proc_refclock_khz = 0;
+    uint32_t attr_freq_dpll_refclock_khz = 0;
     uint32_t attr_proc_dpll_divider = 8;
 
     const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
     auto l_exChiplets = i_target.getChildren<fapi2::TARGET_TYPE_EX>
                         (fapi2::TARGET_STATE_FUNCTIONAL);
 
-    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FREQ_PROC_REFCLOCK_KHZ, FAPI_SYSTEM, attr_freq_proc_refclock_khz)
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FREQ_DPLL_REFCLOCK_KHZ, FAPI_SYSTEM, attr_freq_dpll_refclock_khz)
              , "Attribute read failed");
     //Read the frequency of the quad
     l_address = EQ_QPPM_DPLL_FREQ;
@@ -701,10 +701,10 @@ fapi2::ReturnCode pm_disable_resclk(
     l_data64.extractToRight<EQ_QPPM_DPLL_FREQ_FMULT,
                             EQ_QPPM_DPLL_FREQ_FMULT_LEN>(l_fmult);
 
-    FAPI_INF("EQ_QPPM_DPLL_FREQ_FMULT %04x, attr_freq_proc_refclock_khz %08x, attr_proc_dpll_divider %x",
-             l_fmult, attr_freq_proc_refclock_khz, attr_proc_dpll_divider);
+    FAPI_INF("EQ_QPPM_DPLL_FREQ_FMULT %04x, attr_freq_dpll_refclock_khz %08x, attr_proc_dpll_divider %x",
+             l_fmult, attr_freq_dpll_refclock_khz, attr_proc_dpll_divider);
 
-    l_fmult =  ((l_fmult * attr_freq_proc_refclock_khz ) / attr_proc_dpll_divider) / 1000;
+    l_fmult =  ((l_fmult * attr_freq_dpll_refclock_khz ) / attr_proc_dpll_divider) / 1000;
 
     FAPI_INF("EQ_QPPM_DPLL_FREQ FMULT value %08x", l_fmult);
 
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_pstate_gpe_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_pstate_gpe_init.C
index 8483b9308..01e27f604 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_pstate_gpe_init.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_pstate_gpe_init.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2018                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2019                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -263,10 +263,10 @@ fapi2::ReturnCode pstate_gpe_init(
         auto l_eqChiplets = i_target.getChildren<fapi2::TARGET_TYPE_EQ>
                             (fapi2::TARGET_STATE_FUNCTIONAL);
         fapi2::ATTR_SAFE_MODE_FREQUENCY_MHZ_Type l_attr_safe_mode_freq_mhz;
-        fapi2::ATTR_FREQ_PROC_REFCLOCK_KHZ_Type l_ref_clock_freq_khz;
+        fapi2::ATTR_FREQ_DPLL_REFCLOCK_KHZ_Type l_ref_clock_freq_khz;
         fapi2::ATTR_PROC_DPLL_DIVIDER_Type l_proc_dpll_divider;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SAFE_MODE_FREQUENCY_MHZ, i_target, l_attr_safe_mode_freq_mhz));
-        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FREQ_PROC_REFCLOCK_KHZ, FAPI_SYSTEM, l_ref_clock_freq_khz));
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FREQ_DPLL_REFCLOCK_KHZ, FAPI_SYSTEM, l_ref_clock_freq_khz));
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_DPLL_DIVIDER, i_target, l_proc_dpll_divider));
         // Convert frequency value to a format that needs to be written to the
         // register
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.C
index f3b28a9b4..04c14d2a1 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2018                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2019                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -500,7 +500,7 @@ p9_pm_reset_psafe_update(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_ta
     fapi2::ATTR_VDD_AVSBUS_BUSNUM_Type l_vdd_bus_num;
     fapi2::ATTR_VDD_AVSBUS_RAIL_Type   l_vdd_bus_rail;
     fapi2::ATTR_VDD_BOOT_VOLTAGE_Type       l_vdd_voltage_mv;
-    fapi2::ATTR_FREQ_PROC_REFCLOCK_KHZ_Type l_freq_proc_refclock_khz;
+    fapi2::ATTR_FREQ_DPLL_REFCLOCK_KHZ_Type l_freq_proc_refclock_khz;
     fapi2::ATTR_PROC_DPLL_DIVIDER_Type      l_proc_dpll_divider;
     fapi2::ATTR_SAFE_MODE_NOVDM_UPLIFT_MV_Type l_uplift_mv;
     fapi2::ATTR_EXTERNAL_VRM_STEPSIZE_Type l_ext_vrm_step_size_mv;
@@ -511,7 +511,7 @@ p9_pm_reset_psafe_update(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_ta
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_VDD_AVSBUS_RAIL, i_target, l_vdd_bus_rail));
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_VDD_BOOT_VOLTAGE, i_target, l_vdd_voltage_mv));
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_DPLL_DIVIDER, i_target, l_proc_dpll_divider));
-    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FREQ_PROC_REFCLOCK_KHZ, FAPI_SYSTEM, l_freq_proc_refclock_khz));
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FREQ_DPLL_REFCLOCK_KHZ, FAPI_SYSTEM, l_freq_proc_refclock_khz));
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SAFE_MODE_NOVDM_UPLIFT_MV, i_target, l_uplift_mv));
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_EXTERNAL_VRM_STEPSIZE, FAPI_SYSTEM, l_ext_vrm_step_size_mv));
     l_attr_safe_mode_mv += l_uplift_mv;
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.C b/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.C
index a444af104..0d79ad520 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.C
@@ -2077,7 +2077,7 @@ FAPI_INF("%-60s = 0x%08x %d", #attr_name, iv_attrs.attr_assign, iv_attrs.attr_as
     DATABLOCK_GET_ATTR(ATTR_VOLTAGE_INT_VDD_BIAS_POWERSAVE,  iv_procChip, attr_voltage_int_vdd_bias_powersave);
 
     // Frequency attributes
-    DATABLOCK_GET_ATTR(ATTR_FREQ_PROC_REFCLOCK_KHZ, FAPI_SYSTEM, attr_freq_proc_refclock_khz);
+    DATABLOCK_GET_ATTR(ATTR_FREQ_DPLL_REFCLOCK_KHZ, FAPI_SYSTEM, attr_freq_dpll_refclock_khz);
     DATABLOCK_GET_ATTR(ATTR_FREQ_PB_MHZ,            FAPI_SYSTEM, attr_nest_frequency_mhz);
     DATABLOCK_GET_ATTR(ATTR_FREQ_CORE_CEILING_MHZ,  FAPI_SYSTEM, attr_freq_core_ceiling_mhz);
     DATABLOCK_GET_ATTR(ATTR_SAFE_MODE_FREQUENCY_MHZ,iv_procChip, attr_pm_safe_frequency_mhz);
@@ -2139,7 +2139,7 @@ FAPI_INF("%-60s = 0x%08x %d", #attr_name, iv_attrs.attr_assign, iv_attrs.attr_as
     DATABLOCK_GET_ATTR(ATTR_PROC_R_LOADLINE_VCS_UOHM, iv_procChip, r_loadline_vcs_uohm);
     DATABLOCK_GET_ATTR(ATTR_PROC_R_DISTLOSS_VCS_UOHM, iv_procChip, r_distloss_vcs_uohm);
     DATABLOCK_GET_ATTR(ATTR_PROC_VRM_VOFFSET_VCS_UV,  iv_procChip, vrm_voffset_vcs_uv);
-    DATABLOCK_GET_ATTR(ATTR_FREQ_PROC_REFCLOCK_KHZ,   FAPI_SYSTEM, freq_proc_refclock_khz);
+    DATABLOCK_GET_ATTR(ATTR_FREQ_DPLL_REFCLOCK_KHZ,   FAPI_SYSTEM, freq_proc_refclock_khz);
     DATABLOCK_GET_ATTR(ATTR_PROC_DPLL_DIVIDER,        iv_procChip, proc_dpll_divider);
     // AVSBus ... needed by p9_setup_evid
     //Get WOV attributes
@@ -2169,7 +2169,7 @@ FAPI_INF("%-60s = 0x%08x %d", #attr_name, iv_attrs.attr_assign, iv_attrs.attr_as
                 #_attr_name, iv_attrs._attr_name, iv_attrs._attr_name); \
     }
 
-    SET_DEFAULT(attr_freq_proc_refclock_khz, 133333);
+    SET_DEFAULT(attr_freq_dpll_refclock_khz, 133333);
     SET_DEFAULT(freq_proc_refclock_khz,      133333); // Future: collapse this out
     SET_DEFAULT(attr_ext_vrm_transition_start_ns, EXT_VRM_TRANSITION_START_NS)
     SET_DEFAULT(attr_ext_vrm_transition_rate_inc_uv_per_us, EXT_VRM_TRANSITION_RATE_INC_UV_PER_US)
@@ -2302,7 +2302,7 @@ FAPI_INF("%-60s = 0x%08x %d", #attr_name, iv_attrs.attr_assign, iv_attrs.attr_as
     iv_wov_overv_enabled = true;
 
     //Calculate nest & frequency_step_khz
-    iv_frequency_step_khz = (iv_attrs.attr_freq_proc_refclock_khz /
+    iv_frequency_step_khz = (iv_attrs.attr_freq_dpll_refclock_khz /
                              iv_attrs.attr_proc_dpll_divider);
 
     iv_nest_freq_mhz      = iv_attrs.attr_nest_frequency_mhz;
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.H b/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.H
index 339c47810..e940c1795 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.H
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.H
@@ -119,7 +119,7 @@ typedef struct
     uint32_t attr_proc_r_distloss_vcs_uohm;
     uint32_t attr_proc_vrm_voffset_vcs_uv;
 
-    uint32_t attr_freq_proc_refclock_khz;
+    uint32_t attr_freq_dpll_refclock_khz;
     uint32_t attr_proc_dpll_divider;
     uint32_t attr_nest_frequency_mhz;