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| author | Greg Still <stillgs@us.ibm.com> | 2015-12-22 10:09:28 -0600 |
|---|---|---|
| committer | Stephen Cprek <smcprek@us.ibm.com> | 2016-02-19 17:06:58 -0600 |
| commit | 6824bd0b7b54fd99854a5e360fa113a315b79d95 (patch) | |
| tree | d3f2f76492ce6ce2b241855e4738bb185800a24e /src/import/chips/p9/procedures/hwp/pm/p9_update_ec_eq_state.H | |
| parent | e71e6b1ae873f30f012e9ee9e9bd6650b102318a (diff) | |
| download | talos-hostboot-6824bd0b7b54fd99854a5e360fa113a315b79d95.tar.gz talos-hostboot-6824bd0b7b54fd99854a5e360fa113a315b79d95.zip | |
p9_update_ec_eq_state Level 2
- Both EX and EQ
- Move to only MC groups 0 (All chiplets) and 1 (all cores) being permanent
- suet.scomdef update with MC group register
- Post SUET and Awan test
- Gerrit comments
Change-Id: I940878532a81d2e8008a695fd5a487bc05f3cb75
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22941
Tested-by: Jenkins Server
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Dev-Ready: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/pm/p9_update_ec_eq_state.H')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/pm/p9_update_ec_eq_state.H | 21 |
1 files changed, 20 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_update_ec_eq_state.H b/src/import/chips/p9/procedures/hwp/pm/p9_update_ec_eq_state.H index d355aa1d7..04849c103 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_update_ec_eq_state.H +++ b/src/import/chips/p9/procedures/hwp/pm/p9_update_ec_eq_state.H @@ -7,7 +7,7 @@ /* */ /* EKB Project */ /* */ -/* COPYRIGHT 2015 */ +/* COPYRIGHT 2015,2016 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -37,12 +37,31 @@ #include <fapi2.H> #include <p9_misc_scom_addresses.H> +#include <p9_perv_scom_addresses.H> +#include <p9_quad_scom_addresses.H> + // function pointer typedef definition for HWP call support typedef fapi2::ReturnCode (*p9_update_ec_eq_state_FP_t) ( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + + +namespace p9UpdateECEQ +{ +enum P9_Update_EQ_EC_Constants +{ + MCGR0_CNFG_SETTINGS = 0xE000000000000000ull, // Group 0 + MCGR1_CNFG_SETTINGS = 0xE400000000000000ull, // Group 1 + MCGR2_CNFG_SETTINGS = 0xE800000000000000ull, // Group 2 + MCGR3_CNFG_SETTINGS = 0xEC00000000000000ull, // Group 3 + MCGR_CLEAR_CNFG_SETTINGS = 0xFC00000000000000ull, // Group 7 +}; +} + + + extern "C" { // ----------------------------------------------------------------------------- |
