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authorClaus Michael Olsen <cmolsen@us.ibm.com>2018-05-14 17:51:09 -0500
committerDaniel M. Crowell <dcrowell@us.ibm.com>2018-10-14 13:05:32 -0500
commit52b76be222254e59959db984606c09dae854270b (patch)
treea009b9fbeca0437d3552844bfd55f64147d4a0e1 /src/import/chips/p9/procedures/hwp/pm/p9_scan_ring_util.C
parent62feee748b72ef5f7cb1032964dab2b0686cd916 (diff)
downloadtalos-hostboot-52b76be222254e59959db984606c09dae854270b.tar.gz
talos-hostboot-52b76be222254e59959db984606c09dae854270b.zip
P10 prep: Infrastructure (IS) ring Id metadata and API changes
Gerrit intent: - Applicable for P9 merge (co-req NOT required) - Co-req not req'd for any tests Includes the following changes: - Accommodates initCompiler's needs for additional ring Id APIs to retrieve IS's key ring identifiers, ringId and ringClass, and to align with our enumerated chipId - Elimination of redundancy in and reorg of IS's ring Id lists: RingProperties, GenRingIdList (gone) and ChipletData. - GenRingIdList has been removed. - Expand RingProperties to also include scanScomAddr and ringClass. - Member of ring and chiplet properties structs have been renamed in consistent camel style (no longer using "iv_" anywhere). - Note that with "infrastructure (IS)" we here mean the core infrastructure codes that directly interact with and affect the image. Key_Cronus_Test=XIP_REGRESS Change-Id: I7e92af04edd10c0994718e476f6e7b77c5d124d6 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/59087 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/pm/p9_scan_ring_util.C')
-rw-r--r--src/import/chips/p9/procedures/hwp/pm/p9_scan_ring_util.C6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_scan_ring_util.C b/src/import/chips/p9/procedures/hwp/pm/p9_scan_ring_util.C
index def3c096b..81ad2ad05 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_scan_ring_util.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_scan_ring_util.C
@@ -271,7 +271,7 @@ RingBucket::RingBucket( PlatId i_plat, uint8_t* i_pRingStart, RingDebugMode_t i_
iv_cmnRingMap[ringIndex] = l_quadCmnRings[ringIndex];
}
- for( ringIndex = 0; ringIndex < ( EQ::g_chipletData.iv_num_instance_rings_scan_addrs * MAX_QUADS_PER_CHIP );
+ for( ringIndex = 0; ringIndex < ( EQ::g_chipletData.numInstanceRingsScanAddr * MAX_QUADS_PER_CHIP );
ringIndex++ )
{
iv_instRingMap[ringIndex] = l_quadSpecRings[ringIndex];
@@ -643,12 +643,12 @@ void RingBucket::dumpRings( )
if( iv_plat == PLAT_CME )
{
FAPI_INF("---------------------------------CME Rings---------------------------------------");
- chipletNo = EC::g_chipletData.iv_num_instance_rings_scan_addrs;
+ chipletNo = EC::g_chipletData.numInstanceRingsScanAddr;
}
else if( iv_plat == PLAT_SGPE )
{
FAPI_INF("---------------------------------SGPE Rings--------------------------------------");
- chipletNo = EQ::g_chipletData.iv_num_instance_rings_scan_addrs;
+ chipletNo = EQ::g_chipletData.numInstanceRingsScanAddr;
}
else
{
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