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| author | Sangeetha T S <sangeet2@in.ibm.com> | 2015-11-25 00:16:10 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-09-25 18:13:22 -0400 |
| commit | 6f090d79f7ec21179a984fb59a01b32fc772814c (patch) | |
| tree | 05f58056de6f2812868ee7583505dcd7c6749375 /src/import/chips/p9/procedures/hwp/pm/p9_pm_pss_init.H | |
| parent | d6de3a38537e649d1662d3d13d8d0c1bdac57e1e (diff) | |
| download | talos-hostboot-6f090d79f7ec21179a984fb59a01b32fc772814c.tar.gz talos-hostboot-6f090d79f7ec21179a984fb59a01b32fc772814c.zip | |
Level 2 - p9_pm_pss_init : FAPI 1.0 to FAPI 2.0 transliteration
Change-Id: I1742f794f5191163147dd89986fbb423ca9beb5c
RTC: 140964
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/10800
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29491
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/pm/p9_pm_pss_init.H')
| -rwxr-xr-x | src/import/chips/p9/procedures/hwp/pm/p9_pm_pss_init.H | 41 |
1 files changed, 40 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_pss_init.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_pss_init.H index 4d5ca818c..22a99a1a0 100755 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_pss_init.H +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_pss_init.H @@ -29,9 +29,47 @@ // *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com> // *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com> // *HWP Team: PM -// *HWP Level: 1 +// *HWP Level: 2 // *HWP Consumed by: FSP:HS +/// +/// Procedure Summary: +/// -------------------- +/// One procedure to initialize both P2S and HWC SPIPSS registers to +/// second Procedure is to access APSS or DPSS through P2S Bridge +/// Third procedure is to access APSS or DPSS through HWC (hardware control) +/// +/// High-level procedure flow: +/// ---------------------------------- +/// o INIT PROCEDURE(frame_size,cpol,cpha) +/// - set SPIPSS_ADC_CTRL_REG0(24b) +/// hwctrl_frame_size = 16 +/// - set SPIPSS_ADC_CTRL_REG1 +/// hwctrl_fsm_enable = disable +/// hwctrl_device = APSS +/// hwctrl_cpol = 0 (set idle state = deasserted) +/// hwctrl_cpha = 0 (set 1st edge = capture 2nd edge = change) +/// hwctrl_clock_divider = set to 10Mhz(0x1D) +/// hwctrl_nr_of_frames (4b) = 16 (for auto 2 mode) +/// - set SPIPSS_ADC_CTRL_REG2 +/// hwctrl_interframe_delay = 0x0 +/// - clear SPIPSS_ADC_WDATA_REG +/// - set SPIPSS_P2S_CTRL_REG0 (24b) +/// p2s_frame_size = 16 +/// - set SPIPSS_P2S_CTRL_REG1 +/// p2s_bridge_enable = disable +/// p2s_device = DPSS +/// p2s_cpol = 0 +/// p2s_cpha = 0 +/// p2s_clock_divider = set to 10Mhz +/// p2s_nr_of_frames (1b) = 0 (means 1 frame operation) +/// - set SPIPSS_P2S_CTRL_REG2 +/// p2s_interframe_delay = 0x0 +/// - clear SPIPSS_P2S_WDATA_REG +/// Procedure Prereq: +/// o System clocks are running +/// + #ifndef _P9_PM_PSS_INIT_H_ #define _P9_PM_PSS_INIT_H_ @@ -40,6 +78,7 @@ //------------------------------------------------------------------------------ #include <fapi2.H> #include <p9_pm.H> +#include <p9_misc_scom_addresses.H> typedef fapi2::ReturnCode (*p9_pm_pss_init_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&, |
