JET: Level 1, p9_pm_occ_control

Change-Id: Icc82cfc3d5b1a5a05b0effdd8ccef76ff3abab9b
RTC: 137017
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/21311
Tested-by: Jenkins Server
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25628
Tested-by: FSP CI Jenkins
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

1 files changed, 123 insertions, 0 deletions

diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_control.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_control.H
new file mode 100644
index 000000000..bed5ca166
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_control.H
@@ -0,0 +1,123 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: chips/p9/procedures/hwp/pm/p9_pm_occ_control.H $              */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* EKB Project                                                            */
+/*                                                                        */
+/* COPYRIGHT 2015                                                         */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_pm_occ_control.H
+/// @brief Reset and halt control of the OCC PPC405
+///
+/// *HWP HWP Owner: Greg Still <stillgs @us.ibm.com>
+/// *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com>
+/// *HWP Team: PM
+/// *HWP Level: 1
+/// *HWP Consumed by: FSP:HS
+///
+/// @verbatim
+/// High-level procedure flow:
+/// - process parameters passed to procedure
+/// - If (i_ppc405_boot_ctrl != PPC405_BOOT_NULL)
+///     Initialize boot vector registers in SRAM (SRBV0,1,2,3)
+///     - Initialize SRBV0,1,2 with all 0's (illegal instructions)
+///     - Initialize SRBV0 per passed parameter (i_ppc405_boot_ctrl)
+///       - If (i_ppc405_boot_ctrl = PPC405_BOOT_SRAM)
+///            Initialize to Branch Absolute 0xFFF80010
+///       - If (i_ppc405_boot_ctrl = PPC405_BOOT_MEM)
+///            Initialize to Branch Absolute 0x00000010
+///       - If (i_ppc405_boot_ctrl = PPC405_BOOT_OLD)
+///            initialize to Branch Relative -16
+/// - Write PPC405 rese/halt bits per parameteri_ppc405_reset_ctrl (OCR, OJCFG)
+///     - if PPC405_RESET_NULL , do nothing
+///     - if PPC405_RESET_OFF  , write reset bit to 0 (PPC405 not reset)
+///     - if PPC405_RESET_ON   , write reset bit to 1 (PPC405 reset)
+///     - if PPC405_HALT_OFF   , write halt bit to 0  (PPC405 not halted)
+///     - if PPC405_HALT_ON    , write halt bit to 1  (PPC405 halted)
+///     - if PPC405_RESET_SEQUENCE , Safe halt/reset of OCC (See comments)
+///
+/// Procedure Prereq:
+///   - System clocks are running
+/// @endverbatim
+
+
+#ifndef _P9_OCC_CONTROL_H_
+#define _P9_OCC_CONTROL_H_
+
+// -----------------------------------------------------------------------------
+//  Includes
+// -----------------------------------------------------------------------------
+#include <fapi2.H>
+#include <p9_pm.H>
+#include <p9_misc_scom_addresses.H>
+#include <p9_perv_scom_addresses.H>
+
+// -----------------------------------------------------------------------------
+//  ENUMS
+// -----------------------------------------------------------------------------
+namespace p9occ_ctrl
+{
+enum PPC_CONTROL
+{
+    PPC405_RESET_NULL,       ///< Do nothing
+    PPC405_RESET_OFF,        ///< Deassert the PPC405 reset
+    PPC405_RESET_ON,         ///< Assert the PPC405 reset
+    PPC405_HALT_OFF,         ///< Deassert the PPC405 halt
+    PPC405_HALT_ON,          ///< Assert the PPC405 halt
+    PPC405_RESET_SEQUENCE    ///< Perform the safe halt->reset sequence
+};
+
+enum PPC_BOOT_CONTROL
+{
+    PPC405_BOOT_NULL,        ///< Do nothing
+    PPC405_BOOT_SRAM,        ///< Boot from OCC SRAM
+    PPC405_BOOT_MEM,         ///< Boot from memory
+    PPC405_BOOT_OLD          ///< Deprecated
+};
+}
+
+// function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode (*p9_pm_occ_control_FP_t)
+(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&,
+ const p9occ_ctrl::PPC_CONTROL,
+ const p9occ_ctrl::PPC_BOOT_CONTROL);
+
+extern "C" {
+
+// -----------------------------------------------------------------------------
+//  Function prototype
+// -----------------------------------------------------------------------------
+
+/// @brief Control the operation of the OCC PPC405
+/// @param [in]  i_target            Chip Target
+/// @param [in]  i_ppc405_reset_ctrl PPC405_RESET_NULL   : do nothing
+///                                  PPC405_RESET_OFF    : set ppc405 reset=0
+///                                  PPC405_RESET_ON     : set ppc405 reset=1
+///                                  PPC405_HALT_OFF     : set ppc405 halt=0
+///                                  PPC405_HALT_ON      : set ppc405 halt=1
+///                                  PPC405_RESET_SEQUENCE : gracefully stop by
+///                                                          halt and then reset
+/// @param [in]  i_ppc405_boot_ctrl  PPC405_BOOT_NULL    : do nothing
+///                                  PPC405_BOOT_SRAM    : boot from sram
+///                                  PPC405_BOOT_MEM     : boot from memory
+///                                  PPC405_BOOT_OLD     : boot from sram
+///
+/// @return FAPI_RC_SUCCESS on success or error return code
+    fapi2::ReturnCode p9_pm_occ_control(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const p9occ_ctrl::PPC_CONTROL i_ppc405_reset_ctrl,
+        const p9occ_ctrl::PPC_BOOT_CONTROL i_ppc405_boot_ctrl);
+} // extern "C"
+
+#endif // _P9_OCC_CONTROL_H_