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authorSangeetha T S <sangeet2@in.ibm.com>2015-09-16 01:25:39 -0500
committerDaniel M. Crowell <dcrowell@us.ibm.com>2016-06-10 14:34:58 -0400
commite9536c4b71ab7553a2b5a4021c84c0febfd43f6f (patch)
treec3299334161fad0108eaef29d58309b2f21c0886 /src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.H
parent29cb098e9f15fd79e8445998aa606a1a7ff8b814 (diff)
downloadtalos-hostboot-e9536c4b71ab7553a2b5a4021c84c0febfd43f6f.tar.gz
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JET: Level 2, Make p9_pm_ocb_init FAPI 2.0 compliant
Change-Id: Id898e878cf44ebd2c9f784c7ecff18da6fa7b34c RTC: 128869 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/20550 Tested-by: Jenkins Server Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25627 Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.H')
-rw-r--r--src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.H163
1 files changed, 53 insertions, 110 deletions
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.H
index bf7db2e46..5dc7f4a4d 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.H
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.H
@@ -23,7 +23,7 @@
// *HWP HWP Owner: Amit Kumar <akumar3@us.ibm.com>
// *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com>
// *HWP Team: PM
-// *HWP Level: 1
+// *HWP Level: 2
// *HWP Consumed by: FSP:HS
#ifndef _P9_PM_OCB_INIT_H_
@@ -35,18 +35,15 @@
#include <p9_pm.H>
#include <fapi2.H>
-#if 0
- //Need to verify correct scom addresses are indeed provided in this header.
- #include <misc_scom_addresses.H>
-#endif
+#include <p9_misc_scom_addresses.H>
//------------------------------------------------------------------------------
// Constants definitions
//------------------------------------------------------------------------------
namespace p9ocb
{
-/// @enum P9_OCB_CHAN_NUM
-enum P9_OCB_CHAN_NUM
+/// @enum PM_OCB_CHAN_NUM
+enum PM_OCB_CHAN_NUM
{
OCB_CHAN0 = 0x00, ///< OCB Channel 0
OCB_CHAN1 = 0x01, ///< OCB Channel 1
@@ -54,8 +51,8 @@ enum P9_OCB_CHAN_NUM
OCB_CHAN3 = 0x03 ///< OCB Channel 3
};
-/// @enum P9_OCB_CHAN_TYPE
-enum P9_OCB_CHAN_TYPE
+/// @enum PM_OCB_CHAN_TYPE
+enum PM_OCB_CHAN_TYPE
{
OCB_TYPE_NULL, ///< Do nothing
OCB_TYPE_LIN, ///< Linear w/o address incrementation
@@ -66,23 +63,23 @@ enum P9_OCB_CHAN_TYPE
OCB_TYPE_PULLQ ///< Circular Pull Queue
};
-/// @enum P9_OCB_CHAN_REG
-enum P9_OCB_CHAN_REG
+/// @enum PM_OCB_CHAN_REG
+enum PM_OCB_CHAN_REG
{
OCB_UPD_PIB_REG, ///< Update PIB Register
OCB_UPD_PIB_OCI_REG ///< Update OCI Register
};
-/// @enum P9_OCB_CHAN_OUFLOW
-enum P9_OCB_CHAN_OUFLOW
+/// @enum PM_OCB_CHAN_OUFLOW
+enum PM_OCB_CHAN_OUFLOW
{
OCB_Q_OUFLOW_NULL, ///< Do nothing
OCB_Q_OUFLOW_EN, ///< Overflow/Underflow Enable
OCB_Q_OUFLOW_DIS ///< Overflow/Underflow Disable
};
-/// @enum P9_OCB_ITPTYPE
-enum P9_OCB_ITPTYPE
+/// @enum PM_OCB_ITPTYPE
+enum PM_OCB_ITPTYPE
{
OCB_Q_ITPTYPE_NULL, ///< Overflow/Underflow Disable
OCB_Q_ITPTYPE_FULL, ///< Interrupt on Full
@@ -92,91 +89,15 @@ enum P9_OCB_ITPTYPE
};
} // END OF NAMESPACE p9ocb
-// channel register arrrays
-#if 0
-const uint64_t OCBARn[4] = {OCB0_ADDRESS_0x0006B010,
- OCB1_ADDRESS_0x0006B030,
- OCB2_ADDRESS_0x0006B050,
- OCB3_ADDRESS_0x0006B070
- };
-
-const uint64_t OCBCSRn[4] = {OCB0_STATUS_CONTROL_0x0006B011,
- OCB1_STATUS_CONTROL_0x0006B031,
- OCB2_STATUS_CONTROL_0x0006B051,
- OCB3_STATUS_CONTROL_0x0006B071
- };
-
-const uint64_t OCBCSRn_AND[4] = {OCB0_STATUS_CONTROL_AND_0x0006B012,
- OCB1_STATUS_CONTROL_AND_0x0006B032,
- OCB2_STATUS_CONTROL_AND_0x0006B052,
- OCB3_STATUS_CONTROL_AND_0x0006B072
- };
-
-const uint64_t OCBCSRn_OR[4] = {OCB0_STATUS_CONTROL_OR_0x0006B013,
- OCB1_STATUS_CONTROL_OR_0x0006B033,
- OCB2_STATUS_CONTROL_OR_0x0006B053,
- OCB3_STATUS_CONTROL_OR_0x0006B073
- };
-
-const uint64_t OCBESRn[4] = {OCB0_ERROR_STATUS_0x0006B014,
- OCB1_ERROR_STATUS_0x0006B034,
- OCB2_ERROR_STATUS_0x0006B054,
- OCB3_ERROR_STATUS_0x0006B074
- };
-
-const uint64_t OCBSLBRn[3] = {OCB0_PULL_BASE_0x0006A200,
- OCB1_PULL_BASE_0x0006A210,
- OCB2_PULL_BASE_0x0006A220,
- OCB3_PULL_BASE_0x0006A220
- };
-
-const uint64_t OCBSHBRn[3] = {OCB0_PULL_STATUS_CONTROL_0x0006A201,
- OCB1_PULL_STATUS_CONTROL_0x0006A211,
- OCB2_PULL_STATUS_CONTROL_0x0006A221,
- OCB3_PULL_STATUS_CONTROL_0x0006A221
- };
-
-const uint64_t OCBSLCSn[3] = {OCB0_PUSH_BASE_0x0006A203,
- OCB1_PUSH_BASE_0x0006A213,
- OCB2_PUSH_BASE_0x0006A223,
- OCB3_PUSH_BASE_0x0006A223
- };
-
-const uint64_t OCBSHCSn[3] = {OCB0_PUSH_STATUS_CONTROL_0x0006A204,
- OCB1_PUSH_STATUS_CONTROL_0x0006A214,
- OCB2_PUSH_STATUS_CONTROL_0x0006A224,
- OCB3_PUSH_STATUS_CONTROL_0x0006A224
- };
-
-const uint64_t OCBSESn[3] = {OCB0_STREAM_ERR_STATUS_0x0006A206,
- OCB1_STREAM_ERR_STATUS_0x0006A216,
- OCB2_STREAM_ERR_STATUS_0x0006A226,
- OCB3_STREAM_ERR_STATUS_0x0006A226
- };
-
-// linear window write control
-const uint64_t OCBLWCRn[3] = {OCB0_LIN_WINDOW_CONTROL_0x0006A208,
- OCB1_LIN_WINDOW_CONTROL_0x0006A218,
- OCB2_LIN_WINDOW_CONTROL_0x0006A228,
- OCB3_LIN_WINDOW_CONTROL_0x0006A228
- };
-// linear window write base
-const uint64_t OCBLWSBRn[3] = {OCB0_LIN_WINDOW_BASE_0x0006A20C,
- OCB1_LIN_WINDOW_BASE_0x0006A21C,
- OCB2_LIN_WINDOW_BASE_0x0006A22C,
- OCB3_LIN_WINDOW_BASE_0x0006A22C
- };
-#endif
-
typedef fapi2::ReturnCode (*p9_pm_ocb_init_FP_t) (
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&,
const p9pm::PM_FLOW_MODE,
- const p9ocb::P9_OCB_CHAN_NUM,
- const p9ocb::P9_OCB_CHAN_TYPE,
+ const p9ocb::PM_OCB_CHAN_NUM,
+ const p9ocb::PM_OCB_CHAN_TYPE,
const uint32_t,
const uint8_t,
- const p9ocb::P9_OCB_CHAN_OUFLOW,
- const p9ocb::P9_OCB_ITPTYPE);
+ const p9ocb::PM_OCB_CHAN_OUFLOW,
+ const p9ocb::PM_OCB_ITPTYPE);
extern "C"
{
@@ -188,28 +109,50 @@ extern "C"
///
/// @brief Configure OCB Channels based on mode and parameters passed
///
-/// @param [in] i_target Chip Target
-/// @param [in] i_mode PM_RESET, PM_INIT, or PM_SETUP
-/// @param [in] i_ocb_chan select channel 0-3 to set up
-/// @param [in] i_ocb_type 0=indirect 1=linear stream 2=circular push
-/// 3=circular pull
-/// @param [in] i_ocb_bar 32-bit channel base address(29 bits + "000")
-/// @param [in] i_ocb_q_len 0-31 length of push or pull queue in
-/// (queue_length + 1) * 8B
-/// @param [in] i_ocb_ouflow_en 0=disabled 1=enabled
-/// @param [in] i_ocb_itp_type 0=full 1=not full 2=empty 3=not empty
+/// @param [in] i_target Chip Target
+///
+/// @param [in] i_mode Mode of operation from enum PM_FLOW_MODE.
+/// PM_RESET/PM_INIT/PM_SETUP_ALL
+///
+/// @param [in] i_ocb_chan Channel to setup from enum PM_OCB_CHAN_NUM.
+/// OCB_CHAN0 : OCB Channel 0
+/// OCB_CHAN1 : OCB Channel 1
+/// OCB_CHAN2 : OCB Channel 2
+/// OCB_CHAN3 : OCB Channel 3
+///
+/// @param [in] i_ocb_type Type of channel from PM_OCB_CHAN_TYPE.
+/// OCB_TYPE_LIN:Linear w/o address increment
+/// OCB_TYPE_LINSTR:Linear with address increment
+/// OCB_TYPE_CIRC:Circular mode
+/// OCB_TYPE_PUSHQ:Circular Push Queue
+/// OCB_TYPE_PULLQ:Circular Pull Queue
+///
+/// @param [in] i_ocb_bar 32-bit channel base address(29 bits + "000")
+///
+/// @param [in] i_ocb_q_len 0-31 length of push or pull queue in
+/// (queue_length + 1) * 8B
+///
+/// @param [in] i_ocb_ouflow_en Channel flow control from PM_OCB_CHAN_OUFLOW
+/// OCB_Q_OUFLOW_EN:Overflow/Underflow Enable
+/// OCB_Q_OUFLOW_DIS:Overflow/Underflow Disable
+///
+/// @param [in] i_ocb_itp_type Channel interrupt control from PM_OCB_ITPTYPE
+/// OCB_Q_ITPTYPE_FULL:Interrupt on Full
+/// OCB_Q_ITPTYPE_NOTFULL:Interrupt on Not Full
+/// OCB_Q_ITPTYPE_EMPTY:Interrupt on Empty
+/// OCB_Q_ITPTYPE_NOTEMPTY:Interrupt on Not Empty
///
/// @return FAPI2_RC_SUCCESS if success, else error code.
///
fapi2::ReturnCode p9_pm_ocb_init(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
- const p9pm::PM_FLOW_MODE i_mode,
- const p9ocb::P9_OCB_CHAN_NUM i_ocb_chan,
- const p9ocb::P9_OCB_CHAN_TYPE i_ocb_type,
+ const p9pm::PM_FLOW_MODE i_mode,
+ const p9ocb::PM_OCB_CHAN_NUM i_ocb_chan,
+ const p9ocb::PM_OCB_CHAN_TYPE i_ocb_type,
const uint32_t i_ocb_bar,
const uint8_t i_ocb_q_len,
- const p9ocb::P9_OCB_CHAN_OUFLOW i_ocb_ouflow_en,
- const p9ocb::P9_OCB_ITPTYPE i_ocb_itp_type);
+ const p9ocb::PM_OCB_CHAN_OUFLOW i_ocb_ouflow_en,
+ const p9ocb::PM_OCB_ITPTYPE i_ocb_itp_type);
} // extern "C"
#endif // _P9_PM_OCB_INIT_H_
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