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authorcrgeddes <crgeddes@us.ibm.com>2017-05-24 12:53:46 -0500
committerChristian R. Geddes <crgeddes@us.ibm.com>2017-05-25 18:58:29 -0400
commit5e1b4a600a87238a04cb19284e3385a4c73e80e8 (patch)
tree15793e9c884d114e1317b62921389b10d960acc2 /src/import/chips/p9/procedures/hwp/pm/p9_pm_cme_firinit.C
parent1990ea7f4877e034ff687892de637937e99f0c7b (diff)
downloadtalos-hostboot-5e1b4a600a87238a04cb19284e3385a4c73e80e8.tar.gz
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Reapply "Use query_cache_state hwp before scoming ex's in cme_firinit"
we cannot rely on the HWAS state because during an MPIPL the cores get stopped and the SP doesnt know until an attr sync occurs w/ the platform. We must use the query_cache_state to safely to determine if we can scom the ex targets. This had to be removed because we were incorrectly querying the core EQ state. Change-Id: I248e756b7e305aae0abe1714db610f1e69f2b066 CQ: SW388687 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40926 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40929 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/pm/p9_pm_cme_firinit.C')
-rw-r--r--src/import/chips/p9/procedures/hwp/pm/p9_pm_cme_firinit.C65
1 files changed, 50 insertions, 15 deletions
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_cme_firinit.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_cme_firinit.C
index a21122099..92d5d864c 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_cme_firinit.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_cme_firinit.C
@@ -56,6 +56,7 @@
// Includes
// ----------------------------------------------------------------------
#include <p9_pm_cme_firinit.H>
+#include <p9_query_cache_access_state.H>
// ----------------------------------------------------------------------
// Constant Definitions
@@ -223,34 +224,68 @@ fapi2::ReturnCode pm_cme_fir_reset(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
{
FAPI_IMP("pm_cme_fir_reset start");
-
uint8_t l_firinit_done_flag;
- auto l_exChiplets = i_target.getChildren<fapi2::TARGET_TYPE_EX>
+ auto l_eqChiplets = i_target.getChildren<fapi2::TARGET_TYPE_EQ>
(fapi2::TARGET_STATE_FUNCTIONAL);
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PM_FIRINIT_DONE_ONCE_FLAG,
i_target, l_firinit_done_flag),
"ERROR: Failed to fetch the entry status of FIRINIT");
- for (auto l_ex_chplt : l_exChiplets)
+ for (auto l_eq_chplt : l_eqChiplets)
{
- p9pmFIR::PMFir <p9pmFIR::FIRTYPE_CME_LFIR> l_cmeFir(l_ex_chplt);
+ //We cannot rely on the HWAS state because during an MPIPL
+ //the cores get stopped and the SP doesnt know until an
+ //attr sync occurs with the platform. We must use the
+ //query_cache_state to safely determine if we can scom
+ //the ex targets
+ fapi2::ReturnCode l_rc;
+ bool l_l2_is_scanable = false;
+ bool l_l3_is_scanable = false;
+ bool l_l2_is_scomable = false;
+ bool l_l3_is_scomable = false;
+ uint8_t l_chip_unit_pos;
- if (l_firinit_done_flag == 1)
- {
- FAPI_TRY(l_cmeFir.get(p9pmFIR::REG_FIRMASK),
- "ERROR: Failed to get the CME FIR MASK value");
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS,
+ l_eq_chplt, l_chip_unit_pos),
+ "ERROR: Failed to get the chip unit pos attribute from the eq");
+
+ FAPI_EXEC_HWP(l_rc, p9_query_cache_access_state, l_eq_chplt,
+ l_l2_is_scomable, l_l2_is_scanable,
+ l_l3_is_scomable, l_l3_is_scanable);
+ FAPI_TRY(l_rc, "ERROR: failed to query cache access state for EQ %d",
+ l_chip_unit_pos);
- /* Fetch the CME FIR MASK; Save it to HWP attribute; clear it */
- FAPI_TRY(l_cmeFir.saveMask(),
- "ERROR: Failed to save CME FIR Mask to the attribute");
+ //If this cache isnt scommable continue to the next EQ
+ if(!l_l3_is_scomable)
+ {
+ continue;
}
- FAPI_TRY(l_cmeFir.setAllRegBits(p9pmFIR::REG_FIRMASK),
- "ERROR: Faled to set the CME FIR MASK");
+ auto l_exChiplets = l_eq_chplt.getChildren<fapi2::TARGET_TYPE_EX>
+ (fapi2::TARGET_STATE_FUNCTIONAL);
+
+ for(auto l_ex_chplt : l_exChiplets)
+ {
+ p9pmFIR::PMFir <p9pmFIR::FIRTYPE_CME_LFIR> l_cmeFir(l_ex_chplt);
+
+ if (l_firinit_done_flag == 1)
+ {
+ FAPI_TRY(l_cmeFir.get(p9pmFIR::REG_FIRMASK),
+ "ERROR: Failed to get the CME FIR MASK value");
+
+ /* Fetch the CME FIR MASK; Save it to HWP attribute; clear it */
+ FAPI_TRY(l_cmeFir.saveMask(),
+ "ERROR: Failed to save CME FIR Mask to the attribute");
+ }
+
+ FAPI_TRY(l_cmeFir.setAllRegBits(p9pmFIR::REG_FIRMASK),
+ "ERROR: Faled to set the CME FIR MASK");
+
+ FAPI_TRY(l_cmeFir.put(),
+ "ERROR:Failed to write to the CME FIR MASK");
+ }
- FAPI_TRY(l_cmeFir.put(),
- "ERROR:Failed to write to the CME FIR MASK");
}
fapi_try_exit:
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