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| author | Adam Hale <adam.samuel.hale@ibm.com> | 2017-09-19 17:52:08 -0500 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2017-12-16 15:05:13 -0500 |
| commit | 6e847113eb962160932f50345eaf5fd073f0ec9b (patch) | |
| tree | 2f3de8c2331207e985e6de37d84d59e194a5040f /src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C | |
| parent | 2429064ef8cedc5b930cb49b1b314ed7bab49f82 (diff) | |
| download | talos-hostboot-6e847113eb962160932f50345eaf5fd073f0ec9b.tar.gz talos-hostboot-6e847113eb962160932f50345eaf5fd073f0ec9b.zip | |
Expand PGPE optrace to Main Mem - No fnctl coreq rqmt image build vs hcode
Key_Cronus_Test=PM_REGRESS
Change-Id: I823b350ffe1e07108fbadd4b0456c7188839932f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46480
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48108
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C index 79f504800..1c4aca5e5 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C @@ -1843,6 +1843,10 @@ fapi2::ReturnCode buildPgpeImage( void* const i_pImageIn, Homerlayout_t* i_pChip io_ppmrHdr.g_ppmr_aux_task_offset = io_ppmrHdr.g_ppmr_hcode_offset + PGPE_IMAGE_SIZE; io_ppmrHdr.g_ppmr_aux_task_length = ppeSection.iv_size; + //Used directly for memory access, bit 0 high for PBA access + io_ppmrHdr.g_ppmr_doptrace_offset = 0x80000000 + DOPTRACE_OFFSET; + io_ppmrHdr.g_ppmr_doptrace_length = DOPTRACE_LEN ; + //Finally let us take care of endianess io_ppmrHdr.g_ppmr_bc_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_bc_offset); io_ppmrHdr.g_ppmr_bl_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_bl_offset); @@ -1851,6 +1855,8 @@ fapi2::ReturnCode buildPgpeImage( void* const i_pImageIn, Homerlayout_t* i_pChip io_ppmrHdr.g_ppmr_hcode_length = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_hcode_length); io_ppmrHdr.g_ppmr_aux_task_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_aux_task_offset); io_ppmrHdr.g_ppmr_aux_task_length = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_aux_task_length); + io_ppmrHdr.g_ppmr_doptrace_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_doptrace_offset); + io_ppmrHdr.g_ppmr_doptrace_length = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_doptrace_length); } fapi_try_exit: @@ -2167,6 +2173,10 @@ fapi2::ReturnCode updatePgpeHeader( void* const i_pHomer, CONST_FAPI2_PROC& i_pr FAPI_TRY(calcPPETimebase(&l_ppe_timebase_hz)); pPgpeHdr->g_pgpe_timebase_hz = SWIZZLE_4_BYTE(l_ppe_timebase_hz); + //Deep Operational Trace Constants + pPgpeHdr->g_pgpe_doptrace_offset = SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_doptrace_offset); + pPgpeHdr->g_pgpe_doptrace_length = SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_doptrace_length); + //Finally handling the endianess pPgpeHdr->g_pgpe_gppb_sram_addr = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gppb_sram_addr); pPgpeHdr->g_pgpe_hcode_length = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_hcode_length); @@ -2182,7 +2192,8 @@ fapi2::ReturnCode updatePgpeHeader( void* const i_pHomer, CONST_FAPI2_PROC& i_pr pPgpeHdr->g_wof_table_length = SWIZZLE_4_BYTE(pPgpeHdr->g_wof_table_length); pPgpeHdr->g_pgpe_core_throttle_assert_cnt = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_core_throttle_assert_cnt); pPgpeHdr->g_pgpe_core_throttle_deassert_cnt = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_core_throttle_deassert_cnt); - + pPgpeHdr->g_pgpe_doptrace_offset = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_doptrace_offset); + pPgpeHdr->g_pgpe_doptrace_length = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_doptrace_length); FAPI_DBG("================================PGPE Image Header==========================================") FAPI_DBG("IVPR Address : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_ivpr_addr)); @@ -2201,6 +2212,8 @@ fapi2::ReturnCode updatePgpeHeader( void* const i_pHomer, CONST_FAPI2_PROC& i_pr FAPI_DBG("Core Assert Count : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_core_throttle_assert_cnt)); FAPI_DBG("Core De - Assert Count : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_core_throttle_deassert_cnt)); FAPI_DBG("Auxiliary Control : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_aux_controls)); + FAPI_DBG("Deep OpTrace Offset : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_doptrace_offset)); + FAPI_DBG("Deep OpTrace Length : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_doptrace_length)); FAPI_DBG("Timebase (Hz) : 0x%08X (%d)", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_timebase_hz), SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_timebase_hz)); |
