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| author | Matt K. Light <mklight@us.ibm.com> | 2017-07-06 10:03:26 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-08-14 00:02:45 -0400 |
| commit | fd19d0c74a506e6ef053fa96dabe5f673195049a (patch) | |
| tree | ea278b677aa897206f06d0845d0ec88bf18e407e /src/import/chips/p9/procedures/hwp/perv/p9_start_cbs.C | |
| parent | 70047c0b3b9461a5f15da3d3bd1ec1435f38b8b7 (diff) | |
| download | talos-hostboot-fd19d0c74a506e6ef053fa96dabe5f673195049a.tar.gz talos-hostboot-fd19d0c74a506e6ef053fa96dabe5f673195049a.zip | |
Enable skipping sbefifo reset during p9_start_cbs
For certain systems (RBI/WAFER) under Cronus
skip resetting the sbefifo via cfam register
as it is not available on those FSPs. Use a
new attribute to determine if it is correct
to skip this cfam register write.
Change-Id: I9f63e042f7a3a17b6f7f4c52cd2b4cdf9f2d4aa9
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42811
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Dev-Ready: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42815
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/perv/p9_start_cbs.C')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_start_cbs.C | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_start_cbs.C b/src/import/chips/p9/procedures/hwp/perv/p9_start_cbs.C index 3ddc71375..ac3468162 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_start_cbs.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_start_cbs.C @@ -69,11 +69,16 @@ fapi2::ReturnCode p9_start_cbs(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> fapi2::buffer<uint32_t> l_data32_cbs_cs; int l_timeout = 0; fapi2::buffer<uint8_t> l_read_attr; + fapi2::buffer<uint8_t> l_fifo_reset_skip; + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; FAPI_INF("p9_start_cbs: Entering ..."); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW402019_PIBRESET_DELAY, i_target_chip, l_read_attr)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_START_CBS_FIFO_RESET_SKIP, + FAPI_SYSTEM, l_fifo_reset_skip)); + FAPI_DBG("Clearing Selfboot message register before every boot "); // buffer is init value is 0 FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_SB_MSG_FSI, l_data32)); @@ -163,8 +168,11 @@ fapi2::ReturnCode p9_start_cbs(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> fapi2::delay(P9_PIBRESET_HW_NS_DELAY, P9_PIBRESET_SIM_CYCLE_DELAY); } - FAPI_DBG("FIFO reset"); - FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_FSB_FSB_DOWNFIFO_RESET_FSI, FIFO_RESET)); + if ( !l_fifo_reset_skip ) + { + FAPI_DBG("FIFO reset"); + FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_FSB_FSB_DOWNFIFO_RESET_FSI, FIFO_RESET)); + } if ( i_sbe_start ) { |
