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| author | LiuYangFan <shliuyf@cn.ibm.com> | 2016-04-01 03:25:41 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-08-01 11:56:29 -0400 |
| commit | 47845536df2e76c019b1289fd72d443498b9c102 (patch) | |
| tree | 4b2d9b3e1791d67ed90dd14c762ebbf490b1f853 /src/import/chips/p9/procedures/hwp/perv/p9_ram_getspr.H | |
| parent | 28d4903c629357bca036b0fecb3cf3fb8a6e16a9 (diff) | |
| download | talos-hostboot-47845536df2e76c019b1289fd72d443498b9c102.tar.gz talos-hostboot-47845536df2e76c019b1289fd72d443498b9c102.zip | |
Update RAM procedures.
Changes included:
p9_ram_core:
1. Add special case support for get/put NIA/MSR/CR/FPSCR
2. Add thread stop state check in setup
3. Add error handling when ram_setup/get_reg/put_reg
p9_ram_get_all_reg/p9_ram_put_all_reg:
Add get/put all registers function for test
p9_ram_spr_test:
New file to test SPR, verify with SPY read, for Cronus use
p9_ram_after_checkstop:
New file to test ram after checkstop
p9_ram_addr_error_test:
New file to test ram after bad address access
p9_ram_wrap:
Update to support the new tests
Change-Id: Ia4da55eae26e9f3a667446bc984b358c064fdd8a
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22746
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Jenkins Server
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: PPE CI
Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27696
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/perv/p9_ram_getspr.H')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_ram_getspr.H | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_ram_getspr.H b/src/import/chips/p9/procedures/hwp/perv/p9_ram_getspr.H index e7e01cb2b..3fe4912b1 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_ram_getspr.H +++ b/src/import/chips/p9/procedures/hwp/perv/p9_ram_getspr.H @@ -52,10 +52,10 @@ extern "C" { // Function prototype //----------------------------------------------------------------------------------- /// @brief Implement Get SPR Register by ramming -/// @param[in] i_target => core target -/// @param[in] i_thread => thread number -/// @param[in] i_name => register name -/// @param[out] o_buffer => register value +/// @param[in] i_target => core target +/// @param[in] i_thread => thread number +/// @param[in] i_name => register name +/// @param[out] o_buffer => register value /// @return FAPI_RC_SUCCESS if the setup completes successfully // fapi2::ReturnCode p9_ram_getspr(const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target, @@ -67,3 +67,4 @@ extern "C" { #endif //_P9_RAM_GETSPR_H_ + |
