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| author | Sunil.Kumar <skumar8j@in.ibm.com> | 2016-03-15 00:57:57 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-06-01 14:38:40 -0400 |
| commit | 37bff3473a9c51c5cb0eaa0e36ec71669d0a86c9 (patch) | |
| tree | 26c1c7f18081f43c0dd21590aad0c7553bc5e78e /src/import/chips/p9/procedures/hwp/perv/p9_mem_pll_reset.H | |
| parent | 97b39a92e2e8f49f9f6aadf71c469d9f7ada8fee (diff) | |
| download | talos-hostboot-37bff3473a9c51c5cb0eaa0e36ec71669d0a86c9.tar.gz talos-hostboot-37bff3473a9c51c5cb0eaa0e36ec71669d0a86c9.zip | |
Level 1 HWP p9_mem_pll_reset
Change-Id: Iefc180676a8ec3ffe171bdbbc4489677ad69129a
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22012
Tested-by: Jenkins Server
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25180
Tested-by: FSP CI Jenkins
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/perv/p9_mem_pll_reset.H')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_mem_pll_reset.H | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_mem_pll_reset.H b/src/import/chips/p9/procedures/hwp/perv/p9_mem_pll_reset.H new file mode 100644 index 000000000..81686e8b6 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_mem_pll_reset.H @@ -0,0 +1,57 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/perv/p9_mem_pll_reset.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_mem_pll_reset.H +/// +/// @brief Reset PLL bucket for MC chiplets +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : HB +//------------------------------------------------------------------------------ + + +#ifndef _P9_MEM_PLL_RESET_H_ +#define _P9_MEM_PLL_RESET_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_mem_pll_reset_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// Disable listen_to_sync for MEM chiplet, whenever MEM is not in sync to NEST +/// Move MC PLL into reset state +/// Assert PLL test enable +/// Assert PLL reset +/// Assert PLL bypass" +/// Assert MEM PDLY and DCC bypass +/// Set scan ratio to 1:1 as long as PLL is in bypass mode + +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_mem_pll_reset(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chiplet); +} + +#endif |
