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| author | Adam Hale <adam.samuel.hale@ibm.com> | 2017-08-16 18:32:40 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-09-14 23:34:29 -0400 |
| commit | d79906ed72501bf59cc4f1684aa58b9ee0c987fb (patch) | |
| tree | 169ea3c0268c40ced9f0d9fa4426c22256b8cd3b /src/import/chips/p9/procedures/hwp/nest | |
| parent | 1d36beddc0aa257ad3ba5d25d094ceeeccfca1af (diff) | |
| download | talos-hostboot-d79906ed72501bf59cc4f1684aa58b9ee0c987fb.tar.gz talos-hostboot-d79906ed72501bf59cc4f1684aa58b9ee0c987fb.zip | |
re-enable psave by default
Change-Id: I9adc648572d8af6edaefaf6744cab29cf238b1f5
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44712
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45719
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/nest')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/nest/p9_chiplet_fabric_scominit.C | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_chiplet_fabric_scominit.C b/src/import/chips/p9/procedures/hwp/nest/p9_chiplet_fabric_scominit.C index 010644f77..115b8d13f 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_chiplet_fabric_scominit.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_chiplet_fabric_scominit.C @@ -62,7 +62,7 @@ const uint64_t FBC_IOE_DL_FIR_ACTION0 = 0x0000000000000000ULL; const uint64_t FBC_IOE_DL_FIR_ACTION1 = 0x0303C00000001FFCULL; const uint64_t FBC_IOE_DL_FIR_MASK = 0xFCFC3FFFFFFFE003ULL; - +const uint64_t FBC_IOE_TL_PSAVE_CFG = 0xF1FF01031C000000ULL; //------------------------------------------------------------------------------ // Function definitions //------------------------------------------------------------------------------ @@ -141,6 +141,12 @@ fapi2::ReturnCode p9_chiplet_fabric_scominit(const fapi2::Target<fapi2::TARGET_T "Error from putScom (XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG)"); } + if (l_xbus_chiplets.size()) + { + FAPI_TRY(fapi2::putScom(i_target, PU_PB_PSAVE_CFG, FBC_IOE_TL_PSAVE_CFG), + "Error from putScom (PU_PB_PSAVE_CFG)"); + } + // set FBC optics config mode attribute l_obus_chiplets = i_target.getChildren<fapi2::TARGET_TYPE_OBUS>(); |
