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| author | Luke C. Murray <murrayl@us.ibm.com> | 2017-07-07 17:18:28 -0500 |
|---|---|---|
| committer | Dean Sanner <dsanner@us.ibm.com> | 2017-07-14 08:31:20 -0400 |
| commit | 03d69356357390a3a352ece0209c422ccd3a4e3c (patch) | |
| tree | 809cd6dbd8222f2a5c76b1cb27948d762d9dcc95 /src/import/chips/p9/procedures/hwp/nest/p9_chiplet_scominit.C | |
| parent | d6ef298a9e49c1a7344df3df903db56877465e3f (diff) | |
| download | talos-hostboot-03d69356357390a3a352ece0209c422ccd3a4e3c.tar.gz talos-hostboot-03d69356357390a3a352ece0209c422ccd3a4e3c.zip | |
HW414700 checkstop on UEs and disable core ECC counter
Core
ECP.PC.FIR.THRESHOLD_RESET = 0b00 to disable
CXA, L2, L3, NMMU, NX, VAS, FBC, MC FIR changes to checkstop on UE at source
Change-Id: I4400acb7d3ec68cced49adb5a77fec7bd8356d40
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42887
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42943
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Tested-by: Dean Sanner <dsanner@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/nest/p9_chiplet_scominit.C')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/nest/p9_chiplet_scominit.C | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_chiplet_scominit.C b/src/import/chips/p9/procedures/hwp/nest/p9_chiplet_scominit.C index 8124012a8..9bf3e8aaf 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_chiplet_scominit.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_chiplet_scominit.C @@ -60,6 +60,7 @@ //------------------------------------------------------------------------------ const uint64_t FBC_IOO_TL_FIR_ACTION0 = 0x0000000000000000ULL; const uint64_t FBC_IOO_TL_FIR_ACTION1 = 0x0002400000000000ULL; +const uint64_t FBC_IOO_TL_FIR_ACTION1_HW414700 = 0x0000000000000000ULL; const uint64_t FBC_IOO_TL_FIR_MASK = 0xFF6DB0000FFFFFFFULL; const uint64_t FBC_IOO_DL_FIR_ACTION0 = 0x0000000000000000ULL; @@ -211,9 +212,15 @@ fapi2::ReturnCode p9_chiplet_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PRO if (l_obus_chiplets.size()) { + uint8_t l_hw414700; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW414700, i_target, l_hw414700), + "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_HW414700)"); FAPI_TRY(fapi2::putScom(i_target, PU_IOE_PB_IOO_FIR_ACTION0_REG, FBC_IOO_TL_FIR_ACTION0), "Error from putScom (PU_IOE_PB_IOO_FIR_ACTION0_REG)"); - FAPI_TRY(fapi2::putScom(i_target, PU_IOE_PB_IOO_FIR_ACTION1_REG, FBC_IOO_TL_FIR_ACTION1), + FAPI_TRY(fapi2::putScom(i_target, PU_IOE_PB_IOO_FIR_ACTION1_REG, + (l_hw414700) ? + (FBC_IOO_TL_FIR_ACTION1_HW414700) : + (FBC_IOO_TL_FIR_ACTION1)), "Error from putScom (PU_IOE_PB_IOO_FIR_ACTION1_REG)"); FAPI_TRY(fapi2::putScom(i_target, PU_IOE_PB_IOO_FIR_MASK_REG, FBC_IOO_TL_FIR_MASK), "Error from putScom (PU_IOE_PB_IOO_FIR_MASK_REG)"); |
