Move MRS attributes to eff_config to calc LRDIMMs

Change-Id: Ie2b6d187d67f8bc7ed975e7627fd31ff343e8969
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33774
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33781
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

12 files changed, 771 insertions, 150 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C
index 99cffe51a..19e4c71a1 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* Contributors Listed Below - COPYRIGHT 2016,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -65,7 +65,7 @@ mrs01_data::mrs01_data( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
     FAPI_TRY( mss::vpd_mt_dram_drv_imp_dq_dqs(i_target, &(iv_odic[0])) );
     FAPI_TRY( mss::eff_dram_al(i_target, iv_additive_latency) );
     FAPI_TRY( mss::eff_dram_wr_lvl_enable(i_target, iv_wl_enable) );
-    FAPI_TRY( mss::vpd_mt_dram_rtt_nom(i_target, &(iv_rtt_nom[0])) );
+    FAPI_TRY( mss::eff_dram_rtt_nom(i_target, &(iv_rtt_nom[0])) );
     FAPI_TRY( mss::eff_dram_tdqs(i_target, iv_tdqs) );
     FAPI_TRY( mss::eff_dram_output_buffer(i_target, iv_qoff) );
 
@@ -114,20 +114,24 @@ fapi2::ReturnCode mrs01(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
     // Little table to map Output Driver Imepdance Control. 34Ohm is index 0,
     // 48Ohm is index 1
     // Left bit is A2, right bit is A1
-    constexpr uint8_t odic_map[2] = { 0b00, 0b01 };
+    constexpr uint8_t odic_map[] = { 0b00, 0b01 };
 
-    // Indexed by denominator. So, if RQZ is 240, and you have OHM240, then you're looking
-    // for index 1. So this doesn't correspond directly with the table in the JEDEC spec,
-    // as that's not in "denominator order."
-    //                                   0  RQZ/1  RQZ/2  RQZ/3  RQZ/4  RQZ/5  RQZ/6  RQZ/7
-    constexpr uint8_t rtt_nom_map[8] = { 0, 0b100, 0b010, 0b110, 0b001, 0b101, 0b011, 0b111 };
+    constexpr uint64_t ODIC_LENGTH = 2;
+    constexpr uint64_t ODIC_START_BIT = 7;
+    constexpr uint64_t ADDITIVE_LATENCE_LENGTH = 2;
+    constexpr uint64_t ADDITIVE_LATENCE_START_BIT = 7;
+    constexpr uint64_t RTT_NOM_LENGTH = 3;
+    constexpr uint64_t RTT_NOM_START_BIT = 7;
 
-    size_t l_rtt_nom_index = 0;
 
     fapi2::buffer<uint8_t> l_additive_latency;
     fapi2::buffer<uint8_t> l_odic_buffer;
     fapi2::buffer<uint8_t> l_rtt_nom_buffer;
 
+    //check here to make sure the rank indexes correctly into the attribute array
+    //It's equivalent to mss::index(i_rank) < l_rtt_nom.size() if C arrays had a .size() method
+    fapi2::Assert( mss::index(i_rank) < MAX_RANK_PER_DIMM);
+
     FAPI_ASSERT( ((i_data.iv_odic[mss::index(i_rank)] == fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS_OHM34) ||
                   (i_data.iv_odic[mss::index(i_rank)] == fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS_OHM48)),
                  fapi2::MSS_BAD_MR_PARAMETER()
@@ -141,25 +145,22 @@ fapi2::ReturnCode mrs01(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
     l_odic_buffer = (i_data.iv_odic[mss::index(i_rank)] == fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS_OHM34) ?
                     odic_map[0] : odic_map[1];
 
-    // We have to be careful about 0
-    l_rtt_nom_index = (i_data.iv_rtt_nom[mss::index(i_rank)] == 0) ?
-                      0 : fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_RTT_NOM_OHM240 / i_data.iv_rtt_nom[mss::index(i_rank)];
-
     // Map from RTT_NOM array to the value in the map
-    l_rtt_nom_buffer = rtt_nom_map[l_rtt_nom_index];
+    l_rtt_nom_buffer = i_data.iv_rtt_nom[mss::index(i_rank)];
 
     // Print this here as opposed to the MRS01 ctor as we want to see the specific rtt now information
     FAPI_INF("MR1 rank %d attributes: DLL_ENABLE: 0x%x, ODIC: 0x%x(0x%x), AL: 0x%x, WLE: 0x%x, "
-             "RTT_NOM: 0x%x(0x%x), TDQS: 0x%x, QOFF: 0x%x", i_rank,
+             "RTT_NOM:0x%x, TDQS: 0x%x, QOFF: 0x%x", i_rank,
              i_data.iv_dll_enable, i_data.iv_odic[mss::index(i_rank)], uint8_t(l_odic_buffer), uint8_t(l_additive_latency),
              i_data.iv_wl_enable,
-             i_data.iv_rtt_nom[mss::index(i_rank)], uint8_t(l_rtt_nom_buffer), i_data.iv_tdqs, i_data.iv_qoff);
+             uint8_t(l_rtt_nom_buffer), i_data.iv_tdqs, i_data.iv_qoff);
 
     io_inst.arr0.writeBit<A0>(i_data.iv_dll_enable);
-    mss::swizzle<A1, 2, 7>(l_odic_buffer, io_inst.arr0);
-    mss::swizzle<A3, 2, 7>(fapi2::buffer<uint8_t>(i_data.iv_additive_latency), io_inst.arr0);
+    mss::swizzle<A1, ODIC_LENGTH, ODIC_START_BIT>(l_odic_buffer, io_inst.arr0);
+    mss::swizzle<A3, ADDITIVE_LATENCE_LENGTH, ADDITIVE_LATENCE_START_BIT>(fapi2::buffer<uint8_t>
+            (i_data.iv_additive_latency), io_inst.arr0);
     io_inst.arr0.writeBit<A7>(i_data.iv_wl_enable);
-    mss::swizzle<A8, 3, 7>(l_rtt_nom_buffer, io_inst.arr0);
+    mss::swizzle<A8, RTT_NOM_LENGTH, RTT_NOM_START_BIT>(l_rtt_nom_buffer, io_inst.arr0);
     io_inst.arr0.writeBit<A11>(i_data.iv_tdqs);
     io_inst.arr0.writeBit<A12>(i_data.iv_qoff);
 
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C
index 11a2dced9..1c86e63e5 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* Contributors Listed Below - COPYRIGHT 2016,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -61,7 +61,7 @@ mrs02_data::mrs02_data( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
 {
     FAPI_TRY( mss::eff_dram_lpasr(i_target, iv_lpasr) );
     FAPI_TRY( mss::eff_dram_cwl(i_target, iv_cwl) );
-    FAPI_TRY( mss::vpd_mt_dram_rtt_wr(i_target, &(iv_dram_rtt_wr[0])) );
+    FAPI_TRY( mss::eff_dram_rtt_wr(i_target, &(iv_dram_rtt_wr[0])) );
     FAPI_TRY( mss::eff_write_crc(i_target, iv_write_crc) );
 
     o_rc = fapi2::FAPI2_RC_SUCCESS;
@@ -106,6 +106,13 @@ fapi2::ReturnCode mrs02(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
                         ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst,
                         const uint64_t i_rank)
 {
+    constexpr uint64_t CWL_LENGTH = 3;
+    constexpr uint64_t CWL_START = 7;
+    constexpr uint64_t LPASR_LENGTH = 2;
+    constexpr uint64_t LPASR_START = 7;
+    constexpr uint64_t RTT_WR_LENGTH = 3;
+    constexpr uint64_t RTT_WR_START = 7;
+
     // Index this by subtracting 9 from the CWL attribute value. The table maps CWL attribute value
     // (in clks) to the bit setting in MR2. See the table in the JEDEC spec for the mapping.
     constexpr uint64_t LOWEST_CWL = 9;
@@ -114,7 +121,10 @@ fapi2::ReturnCode mrs02(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
     constexpr uint8_t cwl_map[CWL_COUNT] = { 0b000, 0b001, 0b010, 0b011, 0, 0b100, 0, 0b101, 0, 0b110, 0, 0b111 };
 
     fapi2::buffer<uint8_t> l_cwl_buffer;
-    fapi2::buffer<uint8_t> l_rtt_wr_buffer;
+
+    fapi2::Assert(mss::index(i_rank) < MAX_RANK_PER_DIMM);
+
+    fapi2::buffer<uint8_t> l_rtt_wr_buffer = i_data.iv_dram_rtt_wr[mss::index(i_rank)];
 
     FAPI_ASSERT((i_data.iv_cwl >= LOWEST_CWL) && (i_data.iv_cwl < (LOWEST_CWL + CWL_COUNT)),
                 fapi2::MSS_BAD_MR_PARAMETER()
@@ -126,45 +136,17 @@ fapi2::ReturnCode mrs02(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
 
     l_cwl_buffer = cwl_map[i_data.iv_cwl - LOWEST_CWL];
 
-    switch (i_data.iv_dram_rtt_wr[i_rank])
-    {
-        case fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_RTT_WR_DISABLE:
-            l_rtt_wr_buffer = 0b000;
-            break;
-
-        case fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_RTT_WR_HIGHZ:
-            l_rtt_wr_buffer = 0b011;
-            break;
-
-        case fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_RTT_WR_OHM240:
-            l_rtt_wr_buffer = 0b010;
-            break;
-
-        case fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_RTT_WR_OHM80:
-            l_rtt_wr_buffer = 0b100;
-            break;
-
-        case fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_RTT_WR_OHM120:
-            l_rtt_wr_buffer = 0b001;
-            break;
-
-        default:
-            FAPI_ERR("unknown RTT_WR 0x%x (%s rank %d), dynamic odt off",
-                     i_data.iv_dram_rtt_wr[i_rank], mss::c_str(i_target), i_rank);
-            l_rtt_wr_buffer = 0b000;
-            break;
-    };
 
     // Printed here as opposed to the ctor as it uses the rank information
-    FAPI_INF("MR2 rank %d attributes: LPASR: 0x%x, CWL: 0x%x(0x%x), RTT_WR: 0x%x(0x%x), WRITE_CRC: 0x%x", i_rank,
+    FAPI_INF("MR2 rank %d attributes: LPASR: 0x%x, CWL: 0x%x, RTT_WR: 0x%x(0x%x), WRITE_CRC: 0x%x", i_rank,
              uint8_t(i_data.iv_lpasr), i_data.iv_cwl, uint8_t(l_cwl_buffer),
-             i_data.iv_dram_rtt_wr[i_rank], uint8_t(l_rtt_wr_buffer), i_data.iv_write_crc);
+             uint8_t(l_rtt_wr_buffer), i_data.iv_write_crc);
 
-    mss::swizzle<A3, 3, 7>(l_cwl_buffer, io_inst.arr0);
+    mss::swizzle<A3, CWL_LENGTH, CWL_START>(l_cwl_buffer, io_inst.arr0);
 
-    mss::swizzle<A6, 2, 7>(fapi2::buffer<uint8_t>(i_data.iv_lpasr), io_inst.arr0);
+    mss::swizzle<A6, LPASR_LENGTH, LPASR_START>(fapi2::buffer<uint8_t>(i_data.iv_lpasr), io_inst.arr0);
 
-    mss::swizzle<A9, 3, 7>(l_rtt_wr_buffer, io_inst.arr0);
+    mss::swizzle<A9, RTT_WR_LENGTH, RTT_WR_START>(l_rtt_wr_buffer, io_inst.arr0);
 
     io_inst.arr0.writeBit<A12>(i_data.iv_write_crc);
 
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C
index 5f26b4317..a24421be3 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* Contributors Listed Below - COPYRIGHT 2016,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -48,6 +48,17 @@ namespace mss
 
 namespace ddr4
 {
+enum swizzle : uint64_t
+{
+    MPR_PAGE_LENGTH = 2,
+    MPR_PAGE_START = 7,
+    FINE_REFRESH_LENGTH = 3,
+    FINE_REFRESH_START = 7,
+    CRC_WR_LATENCY_LENGTH = 2,
+    CRC_WR_LATENCY_START = 7,
+    READ_FORMAT_LENGTH = 2,
+    READ_FORMAT_START = 7,
+};
 
 ///
 /// @brief mrs03_data ctor
@@ -120,6 +131,7 @@ fapi2::ReturnCode mrs03(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
                         ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst,
                         const uint64_t i_rank)
 {
+    //Some consts for the swizzle action
     constexpr uint64_t LOWEST_WL = 4;
     constexpr uint64_t WL_COUNT = 3;
     //                                                 4  5  6
@@ -137,15 +149,15 @@ fapi2::ReturnCode mrs03(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
 
     l_crc_wr_latency_buffer = crc_wr_latency_map[i_data.iv_crc_wr_latency - LOWEST_WL];
 
-    mss::swizzle<A0, 2, 7>(fapi2::buffer<uint8_t>(i_data.iv_mpr_page), io_inst.arr0);
+    mss::swizzle<A0, MPR_PAGE_LENGTH, MPR_PAGE_START>(fapi2::buffer<uint8_t>(i_data.iv_mpr_page), io_inst.arr0);
     io_inst.arr0.writeBit<A2>(i_data.iv_mpr_mode);
     io_inst.arr0.writeBit<A3>(i_data.iv_geardown);
     io_inst.arr0.writeBit<A4>(i_data.iv_pda);
     io_inst.arr0.writeBit<A5>(i_data.iv_temp_readout);
 
-    mss::swizzle<A6 , 3, 7>(fapi2::buffer<uint8_t>(i_data.iv_fine_refresh), io_inst.arr0);
-    mss::swizzle<A9 , 2, 7>(l_crc_wr_latency_buffer, io_inst.arr0);
-    mss::swizzle<A11, 2, 7>(fapi2::buffer<uint8_t>(i_data.iv_read_format), io_inst.arr0);
+    mss::swizzle<A6, FINE_REFRESH_LENGTH, FINE_REFRESH_START>(fapi2::buffer<uint8_t>(i_data.iv_fine_refresh), io_inst.arr0);
+    mss::swizzle<A9, CRC_WR_LATENCY_LENGTH, CRC_WR_LATENCY_START>(l_crc_wr_latency_buffer, io_inst.arr0);
+    mss::swizzle<A11, READ_FORMAT_LENGTH, READ_FORMAT_START>(fapi2::buffer<uint8_t>(i_data.iv_read_format), io_inst.arr0);
 
     FAPI_INF("MR3: 0x%016llx", uint64_t(io_inst.arr0));
 
@@ -180,6 +192,7 @@ fapi2::ReturnCode mrs03_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIS
                                       fapi2::buffer<uint8_t>& o_crc_wr_latency_buffer,
                                       fapi2::buffer<uint8_t>& o_read_format)
 {
+
     o_mpr_page = 0;
     o_fine_refresh = 0;
     o_crc_wr_latency_buffer = 0;
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04.C
index f2dd366c2..0f8db6088 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* Contributors Listed Below - COPYRIGHT 2016,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -126,6 +126,9 @@ fapi2::ReturnCode mrs04(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
                         ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst,
                         const uint64_t i_rank)
 {
+    constexpr uint64_t CS_CMD_LATENCY_LENGTH = 3;
+    constexpr uint64_t CS_CMD_LATENCY_START = 7;
+
     constexpr uint64_t CS_CMD_COUNT = 9;
     //                                                       0            3      4      5      6         8
     constexpr uint8_t cs_cmd_latency_map[CS_CMD_COUNT] = { 0b000, 0, 0, 0b001, 0b010, 0b011, 0b100, 0, 0b101 };
@@ -147,7 +150,7 @@ fapi2::ReturnCode mrs04(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
     io_inst.arr0.writeBit<A3>(i_data.iv_temp_ref_mode);
     io_inst.arr0.writeBit<A4>(i_data.iv_vref_mon);
 
-    mss::swizzle<A6, 3, 7>(l_cs_cmd_latency_buffer, io_inst.arr0);
+    mss::swizzle<A6, CS_CMD_LATENCY_LENGTH, CS_CMD_LATENCY_START>(l_cs_cmd_latency_buffer, io_inst.arr0);
     io_inst.arr0.writeBit<A9>(i_data.iv_ref_abort);
     io_inst.arr0.writeBit<A10>(i_data.iv_rd_pre_train_mode);
     io_inst.arr0.writeBit<A11>(i_data.iv_rd_preamble);
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C
index e71034b4e..23831968a 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* Contributors Listed Below - COPYRIGHT 2016,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -68,7 +68,7 @@ mrs05_data::mrs05_data( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
     FAPI_TRY( mss::eff_crc_error_clear(i_target, iv_crc_error_clear) );
     FAPI_TRY( mss::eff_ca_parity_error_status(i_target, iv_ca_parity_error_status) );
     FAPI_TRY( mss::eff_odt_input_buff(i_target, iv_odt_input_buffer) );
-    FAPI_TRY( mss::vpd_mt_dram_rtt_park(i_target, &(iv_rtt_park[0])) );
+    FAPI_TRY( mss::eff_dram_rtt_park(i_target, &(iv_rtt_park[0])) );
     FAPI_TRY( mss::eff_ca_parity(i_target, iv_ca_parity) );
     FAPI_TRY( mss::eff_data_mask(i_target, iv_data_mask) );
     FAPI_TRY( mss::eff_write_dbi(i_target, iv_write_dbi) );
@@ -116,21 +116,27 @@ fapi2::ReturnCode mrs05(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
                         ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst,
                         const uint64_t i_rank)
 {
+    constexpr uint64_t CA_PARITY_LATENCY_LENGTH = 3;
+    constexpr uint64_t CA_PARITY_LATENCY_START = 7;
+    constexpr uint64_t RTT_PARK_LENGTH = 3;
+    constexpr uint64_t RTT_PARK_START = 7;
+
     constexpr uint64_t CA_PARITY_COUNT = 9;
     //                                                             0                4      5      6         8
     constexpr uint8_t ca_parity_latency_map[CA_PARITY_COUNT] = { 0b000, 0, 0, 0, 0b001, 0b010, 0b011, 0, 0b100 };
 
-    // Indexed by denominator. So, if RQZ is 240, and you have OHM240, then you're looking
-    // for index 1. So this doesn't correspond directly with the table in the JEDEC spec,
-    // as that's not in "denominator order."
-    constexpr uint64_t RTT_PARK_COUNT = 8;
-    //                                                 0  RQZ/1  RQZ/2  RQZ/3  RQZ/4  RQZ/5  RQZ/6  RQZ/7
-    constexpr uint8_t rtt_park_map[RTT_PARK_COUNT] = { 0, 0b100, 0b010, 0b110, 0b001, 0b101, 0b011, 0b111 };
+    fapi2::buffer<uint8_t> l_ca_parity_latency_buffer;
 
-    uint8_t l_rtt_park_index = 0;
+    fapi2::buffer<uint8_t> l_rtt_park_buffer = i_data.iv_rtt_park[mss::index(i_rank)];
 
-    fapi2::buffer<uint8_t> l_ca_parity_latency_buffer;
-    fapi2::buffer<uint8_t> l_rtt_park_buffer;
+    //check here to make sure the rank indexes correctly into the attribute array
+    FAPI_ASSERT( (mss::index(i_rank) < MAX_RANK_PER_DIMM),
+                 fapi2::MSS_BAD_MR_PARAMETER()
+                 .set_MR_NUMBER(5)
+                 .set_PARAMETER(RANK)
+                 .set_PARAMETER_VALUE(i_rank)
+                 .set_DIMM_IN_ERROR(i_target),
+                 "Bad value for RTT park: %d (%s)", i_rank, mss::c_str(i_target));
 
     FAPI_ASSERT( (i_data.iv_ca_parity_latency < CA_PARITY_COUNT),
                  fapi2::MSS_BAD_MR_PARAMETER()
@@ -140,35 +146,20 @@ fapi2::ReturnCode mrs05(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
                  .set_DIMM_IN_ERROR(i_target),
                  "Bad value for CA parity latency: %d (%s)", i_data.iv_ca_parity_latency, mss::c_str(i_target));
 
-    FAPI_ASSERT( (i_rank < RTT_PARK_COUNT),
-                 fapi2::MSS_BAD_MR_PARAMETER()
-                 .set_MR_NUMBER(5)
-                 .set_PARAMETER(RTT_PARK)
-                 .set_PARAMETER_VALUE(i_rank)
-                 .set_DIMM_IN_ERROR(i_target),
-                 "Bad value for RTT park: %d (%s)", i_rank, mss::c_str(i_target));
-
     l_ca_parity_latency_buffer = ca_parity_latency_map[i_data.iv_ca_parity_latency];
 
-    // We have to be careful about 0
-    l_rtt_park_index = (i_data.iv_rtt_park[mss::index(i_rank)] == 0) ?
-                       0 : fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_RTT_PARK_240OHM / i_data.iv_rtt_park[mss::index(i_rank)];
-
-    // Map from RTT_PARK array to the value in the map
-    l_rtt_park_buffer = rtt_park_map[l_rtt_park_index];
-
     FAPI_INF("MR5 rank %d attributes: CAPL: 0x%x(0x%x), CRC_EC: 0x%x, CA_PES: 0x%x, ODT_IB: 0x%x "
-             "RTT_PARK: 0x%x(0x%x), CAP: 0x%x, DM: 0x%x, WDBI: 0x%x, RDBI: 0x%x", i_rank,
+             "RTT_PARK: 0x%x, CAP: 0x%x, DM: 0x%x, WDBI: 0x%x, RDBI: 0x%x", i_rank,
              i_data.iv_ca_parity_latency, uint8_t(l_ca_parity_latency_buffer), i_data.iv_crc_error_clear,
              i_data.iv_ca_parity_error_status, i_data.iv_odt_input_buffer,
-             i_data.iv_rtt_park[mss::index(i_rank)], uint8_t(l_rtt_park_buffer), i_data.iv_ca_parity,
+             uint8_t(l_rtt_park_buffer), i_data.iv_ca_parity,
              i_data.iv_data_mask, i_data.iv_write_dbi, i_data.iv_read_dbi);
 
-    mss::swizzle<A0, 3, 7>(l_ca_parity_latency_buffer, io_inst.arr0);
+    mss::swizzle<A0, CA_PARITY_LATENCY_LENGTH, CA_PARITY_LATENCY_START>(l_ca_parity_latency_buffer, io_inst.arr0);
     io_inst.arr0.writeBit<A3>(i_data.iv_crc_error_clear);
     io_inst.arr0.writeBit<A4>(i_data.iv_ca_parity_error_status);
     io_inst.arr0.writeBit<A5>(i_data.iv_odt_input_buffer);
-    mss::swizzle<A6, 3, 7>(l_rtt_park_buffer, io_inst.arr0);
+    mss::swizzle<A6, RTT_PARK_LENGTH, RTT_PARK_START>(l_rtt_park_buffer, io_inst.arr0);
     io_inst.arr0.writeBit<A9>(i_data.iv_ca_parity);
     io_inst.arr0.writeBit<A10>(i_data.iv_data_mask);
     io_inst.arr0.writeBit<A11>(i_data.iv_write_dbi);
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06.C
index 031a7a283..3064909f3 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* Contributors Listed Below - COPYRIGHT 2016,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -104,6 +104,12 @@ fapi2::ReturnCode mrs06(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
                         ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst,
                         const uint64_t i_rank)
 {
+
+    constexpr uint64_t VREFDQ_TRAIN_LENGTH = 6;
+    constexpr uint64_t VREFDQ_TRAIN_START = 7;
+    constexpr uint64_t TCCD_L_LENGTH = 3;
+    constexpr uint64_t TCCD_L_START = 7;
+
     constexpr uint64_t LOWEST_TCCD = 4;
     constexpr uint64_t TCCD_COUNT = 5;
     //                                             4      5     6      7       8
@@ -128,10 +134,10 @@ fapi2::ReturnCode mrs06(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
              i_data.iv_vrefdq_train_range[mss::index(i_rank)],
              i_data.iv_vrefdq_train_enable[mss::index(i_rank)], i_data.iv_tccd_l, uint8_t(l_tccd_l_buffer));
 
-    mss::swizzle<A0, 6, 7>(l_vrefdq_train_value_buffer, io_inst.arr0);
+    mss::swizzle<A0, VREFDQ_TRAIN_LENGTH, VREFDQ_TRAIN_START>(l_vrefdq_train_value_buffer, io_inst.arr0);
     io_inst.arr0.writeBit<A6>(i_data.iv_vrefdq_train_range[mss::index(i_rank)]);
     io_inst.arr0.writeBit<A7>(i_data.iv_vrefdq_train_enable[mss::index(i_rank)]);
-    mss::swizzle<A10, 3, 7>(l_tccd_l_buffer, io_inst.arr0);
+    mss::swizzle<A10, TCCD_L_LENGTH, TCCD_L_START>(l_tccd_l_buffer, io_inst.arr0);
 
     FAPI_INF("MR6: 0x%016llx", uint64_t(io_inst.arr0));
 
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.H
index 22838dc4d..6478a4c74 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -63,6 +63,8 @@ enum mrs_bad_field
     CA_PARITY_LATENCY = 6,
     RTT_PARK = 7,
     TCCD = 8,
+    RANK = 9,
+    RTT_NOM = 10
 };
 
 ///
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C
index 91c8f1f82..6f14f4acd 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* Contributors Listed Below - COPYRIGHT 2016,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -31,6 +31,8 @@
 // *HWP Team: Memory
 // *HWP Level: 2
 // *HWP Consumed by: FSP:HB
+//utils
+#include <math.h>
 
 // fapi2
 #include <fapi2.H>
@@ -48,7 +50,6 @@
 #include <lib/dimm/rank.H>
 #include <lib/utils/conversions.H>
 #include <lib/utils/find.H>
-#include <math.h>
 
 using fapi2::TARGET_TYPE_MCA;
 using fapi2::TARGET_TYPE_MCS;
@@ -236,6 +237,313 @@ fapi_try_exit:
 }
 
 ///
+/// @brief Determines & sets effective config for the RTT_NOM value
+/// @param[in] i_target FAPI2 target
+/// @return fapi2::FAPI2_RC_SUCCESS if okay
+/// @note used for MRS01
+///
+template<>
+fapi2::ReturnCode eff_config::dram_rtt_nom<KIND_RDIMM_DDR4>(const fapi2::Target<TARGET_TYPE_DIMM>& i_target)
+{
+    //Indexing info
+    const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target);
+    const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) );
+    const auto l_dimm_num = index(i_target);
+
+    uint8_t l_decoder_val = 0;
+    uint8_t l_mcs_attrs[PORTS_PER_MCS][MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM] = {};
+
+    //Temp holders to grab attributes to then parse into value for this dimm and rank
+    uint8_t l_rtt_nom[MAX_RANK_PER_DIMM] = {};
+
+    //Size per JEDEC spec
+    constexpr size_t RTT_NOM_SIZE = 8;
+    // Indexed by denominator. So, if RQZ is 240, and you have OHM240, then you're looking
+    // for index 1. So this doesn't correspond directly with the table in the JEDEC spec,
+    // as that's not in "denominator order."
+    //                                   0  RQZ/1  RQZ/2  RQZ/3  RQZ/4  RQZ/5  RQZ/6  RQZ/7
+    constexpr uint8_t rtt_nom_map[] = { 0, 0b100, 0b010, 0b110, 0b001, 0b101, 0b011, 0b111 };
+
+    size_t l_rtt_nom_index = 0;
+    std::vector< uint64_t > l_ranks;
+
+    FAPI_TRY( mss::vpd_mt_dram_rtt_nom(i_target, &(l_rtt_nom[0])) );
+    FAPI_TRY( eff_dram_rtt_nom(l_mcs, &l_mcs_attrs[0][0][0]) );
+
+    //Calculate the value for each rank and store in attribute
+
+    FAPI_TRY(mss::rank::ranks(i_target, l_ranks));
+
+    for (const auto& l_rank : l_ranks)
+    {
+        // We have to be careful about 0
+        l_rtt_nom_index = (l_rtt_nom[mss::index(l_rank)] == 0) ?
+                          0 : fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_RTT_NOM_OHM240 / l_rtt_nom[mss::index(l_rank)];
+
+        //Make sure it's a valid index
+        FAPI_ASSERT( (l_rtt_nom_index < RTT_NOM_SIZE),
+                     fapi2::MSS_BAD_MR_PARAMETER()
+                     .set_MR_NUMBER(5)
+                     .set_PARAMETER(RTT_NOM)
+                     .set_PARAMETER_VALUE(l_rtt_nom_index)
+                     .set_DIMM_IN_ERROR(i_target),
+                     "Bad value for RTT NOM: %d (%s)", l_rank, mss::c_str(i_target));
+
+
+        // Map from RTT_NOM array to the value in the map
+        l_decoder_val = rtt_nom_map[l_rtt_nom_index];
+
+        //Store value and move to next rank
+        l_mcs_attrs[l_port_num][l_dimm_num][mss::index(l_rank)] = l_decoder_val;
+    }
+
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_RTT_NOM, l_mcs, l_mcs_attrs) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Determines & sets effective config for the RTT_NOM value
+/// @param[in] i_target FAPI2 target
+/// @return fapi2::FAPI2_RC_SUCCESS if okay
+/// @note used for MRS01
+///
+template<>
+fapi2::ReturnCode eff_config::dram_rtt_nom<KIND_LRDIMM_DDR4>(const fapi2::Target<TARGET_TYPE_DIMM>& i_target)
+{
+    //Indexing info
+    const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target);
+    const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) );
+    const auto l_dimm_num = index(i_target);
+    std::vector< uint64_t > l_ranks;
+
+
+    uint8_t l_decoder_val = 0;
+    uint8_t l_mcs_attrs[PORTS_PER_MCS][MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM] = {};
+    FAPI_TRY( eff_dram_rtt_nom(l_mcs, &l_mcs_attrs[0][0][0]) );
+
+    //Get the value from the LRDIMM SPD
+    FAPI_TRY( iv_pDecoder->iv_module_decoder->dram_rtt_nom( iv_freq, l_decoder_val));
+
+    //Plug into every rank position for the attribute so it'll fit the same style as the RDIMM value
+    //Same value for every rank for LRDIMMs
+    FAPI_TRY(mss::rank::ranks(i_target, l_ranks));
+
+    for (const auto& l_rank : l_ranks)
+    {
+        l_mcs_attrs[l_port_num][l_dimm_num][mss::index(l_rank)] = l_decoder_val;
+    }
+
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_RTT_NOM, l_mcs, l_mcs_attrs) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+///
+/// @brief Determines & sets effective config for the RTT_WR value from SPD
+/// @param[in] i_target FAPI2 target
+/// @return fapi2::FAPI2_RC_SUCCESS if okay
+/// @note used for MRS02
+///
+template<>
+fapi2::ReturnCode eff_config::dram_rtt_wr<KIND_RDIMM_DDR4>(const fapi2::Target<TARGET_TYPE_DIMM>& i_target)
+{
+    const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target);
+    const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) );
+    const auto l_dimm_num = index(i_target);
+    std::vector< uint64_t > l_ranks;
+
+
+    uint8_t l_decoder_val = 0;
+    uint8_t l_mcs_attrs[PORTS_PER_MCS][MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM] = {};
+
+    FAPI_TRY( eff_dram_rtt_wr(l_mcs, &l_mcs_attrs[0][0][0]) );
+
+    //Get RTT_WR from VPD
+    uint8_t l_dram_rtt_wr[MAX_RANK_PER_DIMM];
+    FAPI_TRY( mss::vpd_mt_dram_rtt_wr(i_target, &(l_dram_rtt_wr[0])) );
+
+    //Calculate the value for each rank and store in attribute
+    FAPI_TRY(mss::rank::ranks(i_target, l_ranks));
+
+    for (const auto& l_rank : l_ranks)
+    {
+        const auto l_index = mss::index(l_rank);
+
+        switch (l_dram_rtt_wr[l_index])
+        {
+            case fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_RTT_WR_DISABLE:
+                l_decoder_val = 0b000;
+                break;
+
+            case fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_RTT_WR_HIGHZ:
+                l_decoder_val = 0b011;
+                break;
+
+            case fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_RTT_WR_OHM240:
+                l_decoder_val = 0b010;
+                break;
+
+            case fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_RTT_WR_OHM80:
+                l_decoder_val = 0b100;
+                break;
+
+            case fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_RTT_WR_OHM120:
+                l_decoder_val = 0b001;
+                break;
+
+            default:
+                FAPI_ERR("unknown RTT_WR 0x%x (%s rank %d), dynamic odt off",
+                         l_dram_rtt_wr[l_index], mss::c_str(i_target), l_rank);
+                l_decoder_val = 0b000;
+                break;
+        };
+
+        //Store value and move to next rank
+        l_mcs_attrs[l_port_num][l_dimm_num][mss::index(l_rank)] = l_decoder_val;
+    }
+
+    //Set the attribute
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_RTT_WR, l_mcs, l_mcs_attrs) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Determines & sets effective config for the RTT_WR value from SPD
+/// @param[in] i_target FAPI2 target
+/// @return fapi2::FAPI2_RC_SUCCESS if okay
+/// @note used for MRS02
+///
+template<>
+fapi2::ReturnCode eff_config::dram_rtt_wr<KIND_LRDIMM_DDR4>(const fapi2::Target<TARGET_TYPE_DIMM>& i_target)
+{
+    const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target);
+    const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) );
+    const auto l_dimm_num = index(i_target);
+    std::vector< uint64_t > l_ranks;
+
+
+    uint8_t l_decoder_val = 0;
+    uint8_t l_mcs_attrs[PORTS_PER_MCS][MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM] = {};
+
+    //Get the value from the LRDIMM SPD
+    FAPI_TRY( iv_pDecoder->iv_module_decoder->dram_rtt_wr( iv_freq, l_decoder_val));
+
+    //Plug into every rank position for the attribute so it'll fit the same style as the RDIMM value
+    //Same value for every rank for LRDIMMs
+    FAPI_TRY(mss::rank::ranks(i_target, l_ranks));
+
+    for (const auto& l_rank : l_ranks)
+    {
+        l_mcs_attrs[l_port_num][l_dimm_num][mss::index(l_rank)] = l_decoder_val;
+    }
+
+    //Set the attribute
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_RTT_WR, l_mcs, l_mcs_attrs) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Determines & sets effective config for the RTT_PARK value from SPD
+/// @param[in] i_target FAPI2 target
+/// @return fapi2::FAPI2_RC_SUCCESS if okay
+/// @note used for MRS05
+///
+template <>
+fapi2::ReturnCode eff_config::dram_rtt_park<KIND_RDIMM_DDR4>(const fapi2::Target<TARGET_TYPE_DIMM>& i_target)
+{
+    //Indexing info
+    const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target);
+    const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) );
+    const auto l_dimm_num = index(i_target);
+    std::vector< uint64_t > l_ranks;
+
+    uint8_t l_mcs_attrs[PORTS_PER_MCS][MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM] = {};
+
+    // Indexed by denominator. So, if RQZ is 240, and you have OHM240, then you're looking
+    // for index 1. So this doesn't correspond directly with the table in the JEDEC spec,
+    // as that's not in "denominator order."
+    constexpr uint64_t RTT_PARK_COUNT = 8;
+    //                                                 0  RQZ/1  RQZ/2  RQZ/3  RQZ/4  RQZ/5  RQZ/6  RQZ/7
+    constexpr uint8_t rtt_park_map[RTT_PARK_COUNT] = { 0, 0b100, 0b010, 0b110, 0b001, 0b101, 0b011, 0b111 };
+
+    uint8_t l_rtt_park[MAX_RANK_PER_DIMM];
+
+    FAPI_TRY( mss::vpd_mt_dram_rtt_park(i_target, &(l_rtt_park[0])) );
+    FAPI_TRY( eff_dram_rtt_park(l_mcs, &l_mcs_attrs[0][0][0]) );
+
+    //Calculate the value for each rank and store in attribute
+    FAPI_TRY(mss::rank::ranks(i_target, l_ranks));
+
+
+    for (const auto& l_rank : l_ranks)
+    {
+        const auto l_index = mss::index(l_rank);
+
+        // We have to be careful about 0
+        uint8_t l_rtt_park_index = (l_rtt_park[l_index] == 0) ?
+                                   0 : fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_RTT_PARK_240OHM / l_rtt_park[l_index];
+
+        FAPI_ASSERT( (l_rtt_park_index < RTT_PARK_COUNT),
+                     fapi2::MSS_BAD_MR_PARAMETER()
+                     .set_MR_NUMBER(5)
+                     .set_PARAMETER(RTT_PARK)
+                     .set_PARAMETER_VALUE(l_rank)
+                     .set_DIMM_IN_ERROR(i_target),
+                     "Bad value for RTT park: %d (%s)", l_rank, mss::c_str(i_target));
+
+        // Map from RTT_PARK array to the value in the map
+        l_mcs_attrs[l_port_num][l_dimm_num][l_index] = rtt_park_map[l_rtt_park_index];
+    }
+
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_RTT_PARK, l_mcs, l_mcs_attrs) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Determines & sets effective config for the RTT_PARK value from SPD
+/// @param[in] i_target FAPI2 target
+/// @return fapi2::FAPI2_RC_SUCCESS if okay
+/// @note used for MRS05
+///
+template <>
+fapi2::ReturnCode eff_config::dram_rtt_park<KIND_LRDIMM_DDR4>(const fapi2::Target<TARGET_TYPE_DIMM>& i_target)
+{
+//Indexing info
+    const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target);
+    const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) );
+    const auto l_dimm_num = index(i_target);
+
+    uint8_t l_mcs_attrs[PORTS_PER_MCS][MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM] = {};
+    uint8_t l_decoder_val_01 = 0;
+    uint8_t l_decoder_val_23 = 0;
+
+    FAPI_TRY( eff_dram_rtt_park(l_mcs, &l_mcs_attrs[0][0][0]) );
+
+    //Get the value from the LRDIMM SPD
+    FAPI_TRY( iv_pDecoder->iv_module_decoder->dram_rtt_park_ranks0_1( iv_freq, l_decoder_val_01));;
+    FAPI_TRY( iv_pDecoder->iv_module_decoder->dram_rtt_park_ranks2_3( iv_freq, l_decoder_val_23));;
+
+    l_mcs_attrs[l_port_num][l_dimm_num][0] = l_decoder_val_01;
+    l_mcs_attrs[l_port_num][l_dimm_num][1] = l_decoder_val_01;
+    l_mcs_attrs[l_port_num][l_dimm_num][2] = l_decoder_val_23;
+    l_mcs_attrs[l_port_num][l_dimm_num][3] = l_decoder_val_23;
+
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_RTT_PARK, l_mcs, l_mcs_attrs) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
 /// @brief Determines & sets effective config for dram density
 /// @param[in] i_target FAPI2 target
 /// @return fapi2::FAPI2_RC_SUCCESS if okay
@@ -1137,16 +1445,12 @@ fapi2::ReturnCode eff_config::dimm_rc10(const fapi2::Target<TARGET_TYPE_DIMM>& i
     const auto l_port_num = index(l_mca);
     const auto l_dimm_num = index(i_target);
 
-    uint64_t l_freq = 0;
-
     // Retrieve MCS attribute data
     uint8_t l_attrs_dimm_rc10[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
     FAPI_TRY( eff_dimm_ddr4_rc10(l_mcs, &l_attrs_dimm_rc10[0][0]) );
 
-    // Update MCS attribute
-    FAPI_TRY( mss::freq( mss::find_target<TARGET_TYPE_MCBIST>(i_target), l_freq ) );
 
-    switch(l_freq)
+    switch(iv_freq)
     {
         case fapi2::ENUM_ATTR_MSS_FREQ_MT1866:
             l_attrs_dimm_rc10[l_port_num][l_dimm_num] = rc10_encode::DDR4_1866;
@@ -1165,7 +1469,7 @@ fapi2::ReturnCode eff_config::dimm_rc10(const fapi2::Target<TARGET_TYPE_DIMM>& i
             break;
 
         default:
-            FAPI_ERR("Invalid frequency for rc10 encoding received: %d", l_freq);
+            FAPI_ERR("Invalid frequency for rc10 encoding received: %d", iv_freq);
             return fapi2::FAPI2_RC_FALSE;
             break;
     }
@@ -1431,16 +1735,12 @@ fapi2::ReturnCode eff_config::dimm_rc3x(const fapi2::Target<TARGET_TYPE_DIMM>& i
     const auto l_port_num = index(l_mca);
     const auto l_dimm_num = index(i_target);
 
-    uint64_t l_freq = 0;
     uint8_t l_attrs_dimm_rc_3x[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
 
     // Retrieve MCS attribute data
     FAPI_TRY( eff_dimm_ddr4_rc_3x(l_mcs, &l_attrs_dimm_rc_3x[0][0]) );
 
-    // Update MCS attribute
-    FAPI_TRY( freq(find_target<TARGET_TYPE_MCBIST>(l_mcs), l_freq) );
-
-    switch(l_freq)
+    switch(iv_freq)
     {
         case fapi2::ENUM_ATTR_MSS_FREQ_MT1866:
             l_attrs_dimm_rc_3x[l_port_num][l_dimm_num] = rc3x_encode::MT1860_TO_MT1880;
@@ -1459,7 +1759,7 @@ fapi2::ReturnCode eff_config::dimm_rc3x(const fapi2::Target<TARGET_TYPE_DIMM>& i
             break;
 
         default:
-            FAPI_ERR("Invalid frequency for rc_3x encoding received: %d", l_freq);
+            FAPI_ERR("Invalid frequency for rc_3x encoding received: %d", iv_freq);
             return fapi2::FAPI2_RC_FALSE;
             break;
     }
@@ -1882,13 +2182,11 @@ fapi2::ReturnCode eff_config::dram_cwl(const fapi2::Target<TARGET_TYPE_DIMM>& i_
 
     std::vector<uint8_t> l_attrs_cwl(PORTS_PER_MCS, 0);
     uint8_t l_cwl = 0;
-    uint64_t l_freq;
     uint8_t l_preamble = 0;
 
     // Targets
     const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target);
     const auto l_mca = find_target<TARGET_TYPE_MCA>(i_target);
-    const auto l_mcbist = find_target <TARGET_TYPE_MCBIST>(i_target);
     // Current index
     const auto l_port_num = index(l_mca);
 
@@ -1906,23 +2204,21 @@ fapi2::ReturnCode eff_config::dram_cwl(const fapi2::Target<TARGET_TYPE_DIMM>& i_
                  mss::c_str(i_target),
                  l_preamble );
 
-    FAPI_TRY( mss::freq(l_mcbist, l_freq) );
-
     // Using an if branch because a ternary conditional wasn't working with params for find_value_from_key
     if (l_preamble == 0)
     {
         FAPI_TRY( mss::find_value_from_key( CWL_TABLE_1,
-                                            l_freq, l_cwl),
+                                            iv_freq, l_cwl),
                   "Failed finding CAS Write Latency (cwl), freq: %d, preamble %d",
-                  l_freq,
+                  iv_freq,
                   l_preamble);
     }
     else
     {
         FAPI_TRY( mss::find_value_from_key( CWL_TABLE_2,
-                                            l_freq, l_cwl),
+                                            iv_freq, l_cwl),
                   "Failed finding CAS Write Latency (cwl), freq: %d, preamble %d",
-                  l_freq,
+                  iv_freq,
                   l_preamble);
 
     }
@@ -2992,7 +3288,6 @@ fapi_try_exit:
 fapi2::ReturnCode eff_config::zqcal_interval(const fapi2::Target<TARGET_TYPE_DIMM>& i_target)
 {
     std::vector<uint32_t> l_attrs_zqcal_interval(PORTS_PER_MCS, 0);
-    uint64_t l_freq = 0;
 
     // Targets
     const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target);
@@ -3001,7 +3296,6 @@ fapi2::ReturnCode eff_config::zqcal_interval(const fapi2::Target<TARGET_TYPE_DIM
     // Current index
     const auto l_port_num = index(l_mca);
 
-    FAPI_TRY( mss::freq(find_target<fapi2::TARGET_TYPE_MCBIST>(l_mcs), l_freq));
     FAPI_TRY( eff_zqcal_interval(l_mcs, l_attrs_zqcal_interval.data()) );
 
     // Calculate ZQCAL Interval based on the following equation from Ken:
@@ -3010,7 +3304,7 @@ fapi2::ReturnCode eff_config::zqcal_interval(const fapi2::Target<TARGET_TYPE_DIM
     //     (1.5 * 10) + (0.15 * 150)
     //  (13333 * ATTR_MSS_FREQ) / 2
 
-    l_attrs_zqcal_interval[l_port_num] = 13333 * l_freq / 2;
+    l_attrs_zqcal_interval[l_port_num] = 13333 * iv_freq / 2;
 
 
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_ZQCAL_INTERVAL,
@@ -3030,7 +3324,6 @@ fapi_try_exit:
 fapi2::ReturnCode eff_config::memcal_interval(const fapi2::Target<TARGET_TYPE_DIMM>& i_target)
 {
     std::vector<uint32_t> l_attrs_memcal_interval(PORTS_PER_MCS, 0);
-    uint64_t l_freq = 0;
 
     // Targets
     const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target);
@@ -3039,13 +3332,11 @@ fapi2::ReturnCode eff_config::memcal_interval(const fapi2::Target<TARGET_TYPE_DI
     // Current index
     const auto l_port_num = index(l_mca);
 
-    FAPI_TRY( mss::freq(find_target<fapi2::TARGET_TYPE_MCBIST>(i_target), l_freq));
-
     FAPI_TRY( eff_memcal_interval(l_mcs, l_attrs_memcal_interval.data()) );
 
     // Calculate MEMCAL Interval based on 1sec interval across all bits per DP16
     // (62500 * ATTR_MSS_FREQ) / 2
-    l_attrs_memcal_interval[l_port_num] = 62500 * l_freq / 2;
+    l_attrs_memcal_interval[l_port_num] = 62500 * iv_freq / 2;
 
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_MEMCAL_INTERVAL,
                             l_mcs,
@@ -3664,7 +3955,7 @@ fapi2::ReturnCode eff_config::decode_vpd(const fapi2::Target<TARGET_TYPE_MCS>& i
 
     // We need to set up all VPD info before calling getVPD, the API assumes this
     // For MR we need to tell the VPDInfo the frequency (err ... mt/s - why is this mhz?)
-    FAPI_TRY( mss::freq(find_target<TARGET_TYPE_MCBIST>(i_target), l_vpd_info.iv_freq_mhz) );
+    l_vpd_info.iv_freq_mhz = iv_freq;
     FAPI_INF("%s. VPD info - dimm data rate: %d MT/s", mss::c_str(i_target), l_vpd_info.iv_freq_mhz);
 
     // Make sure to create 0 filled blobs for all the possible blobs, not just for the
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.H b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.H
index e6f780d88..47128b68d 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* Contributors Listed Below - COPYRIGHT 2016,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -47,6 +47,7 @@
 #include <lib/eff_config/timing.H>
 #include <lib/utils/conversions.H>
 #include <lib/utils/find.H>
+#include <lib/shared/mss_kind.H>
 namespace mss
 {
 
@@ -60,7 +61,7 @@ class eff_config
         //TK - Make this constructor take this as param - AAM
         std::shared_ptr<spd::decoder> iv_pDecoder;
         int64_t iv_tCK_in_ps;
-
+        uint64_t iv_freq;
         // Assists testing with write ability on these MRW
         // settings that are normally NOT writable
         // using attribute accessors
@@ -68,23 +69,6 @@ class eff_config
         uint8_t iv_refresh_mode;
         uint8_t iv_temp_refresh_range;
 
-        //TODO: RTC 159777: Change eff_config class to use iv's for mcs, port and dimm position
-
-        ///
-        /// @brief Constructor
-        /// @param[in] i_target the fapi2::Target which we're configuring (DIMM)
-        /// @param[out] o_rc a return code which determines the success of the constructor
-        ///
-        eff_config( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, fapi2::ReturnCode& o_rc )
-        {
-            FAPI_TRY( clock_period(i_target, iv_tCK_in_ps), "Failed to calculate clock period (tCK)" );
-            FAPI_INF("Calculated clock period (tCK): %d  on DIMM %s", iv_tCK_in_ps, mss::c_str(i_target));
-
-        fapi_try_exit:
-            o_rc = fapi2::current_err;
-            return;
-        }
-
         ///
         /// @brief Constructor
         /// @param[in] i_target  the fapi2::Target which we're configuring (MCS)
@@ -93,10 +77,13 @@ class eff_config
         eff_config( const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, fapi2::ReturnCode& o_rc )
         {
             FAPI_TRY( clock_period(i_target, iv_tCK_in_ps), "Failed to calculate clock period (tCK)" );
+            FAPI_TRY( mss::freq(find_target<fapi2::TARGET_TYPE_MCBIST>(i_target), iv_freq));
             FAPI_TRY( mss::mrw_temp_refresh_range(iv_temp_refresh_range), "Failed mrw_temp_refresh_range()" );
             FAPI_TRY( mss::mrw_fine_refresh_mode(iv_refresh_mode), "Failed mrw_fine_refresh_mode()" );
 
             FAPI_INF( "Calculated clock period -  tCK (ps): %d for  %s", iv_tCK_in_ps, mss::c_str(i_target) );
+            FAPI_INF("Calculated frequency: %d  on DIMM %s", iv_freq, mss::c_str(i_target));
+
 
         fapi_try_exit:
             o_rc = fapi2::current_err;
@@ -185,6 +172,36 @@ class eff_config
         fapi2::ReturnCode dram_width(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target);
 
         ///
+        /// @brief Determines & sets effective config for the RTT_NOM value from SPD
+        /// @tparam kind_t dimm_kind value
+        /// @param[in] i_target FAPI2 target
+        /// @return fapi2::FAPI2_RC_SUCCESS if okay
+        /// @note used for MRS01
+        ///
+        template<mss::kind_t>
+        fapi2::ReturnCode dram_rtt_nom(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target);
+
+        ///
+        /// @brief Determines & sets effective config for the RTT_NOM value from SPD
+        /// @tparam kind_t dimm_kind value
+        /// @param[in] i_target FAPI2 target
+        /// @return fapi2::FAPI2_RC_SUCCESS if okay
+        /// @note used for MRS02
+        ///
+        template<mss::kind_t>
+        fapi2::ReturnCode dram_rtt_wr(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target);
+
+        ///
+        /// @brief Determines & sets effective config for the RTT_PARK value from SPD
+        /// @tparam kind_t dimm_kind value
+        /// @param[in] i_target FAPI2 target
+        /// @return fapi2::FAPI2_RC_SUCCESS if okay
+        /// @note used for MRS05
+        ///
+        template <mss::kind_t>
+        fapi2::ReturnCode dram_rtt_park(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target);
+
+        ///
         /// @brief Determines & sets effective config for dimm rcd mirror mode
         /// @param[in] i_target FAPI2 target
         /// @return fapi2::FAPI2_RC_SUCCESS if okay
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
index 801f392b4..10908f668 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* Contributors Listed Below - COPYRIGHT 2016,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -10596,6 +10596,285 @@ fapi_try_exit:
 }
 
 ///
+/// @brief ATTR_EFF_DRAM_RTT_NOM getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
+/// @param[out] uint8_t* memory to store the value
+/// @note Generated by gen_accessors.pl generateParameters (A)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  RTT_NOM value read to be programmed into MRS02 For RDIMMS, this is based off of
+/// the VPD For LRDIMMS, this comes from the
+/// SPD
+///
+inline fapi2::ReturnCode eff_dram_rtt_nom(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t* o_array)
+{
+    if (o_array == nullptr)
+    {
+        FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
+        return fapi2::FAPI2_RC_INVALID_PARAMETER;
+    }
+
+    uint8_t l_value[2][2][4];
+    auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
+    auto l_mcs = l_mca.getParent<fapi2::TARGET_TYPE_MCS>();
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DRAM_RTT_NOM, l_mcs, l_value) );
+    memcpy(o_array, &(l_value[mss::index(l_mca)][mss::index(i_target)][0]), 4);
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_EFF_DRAM_RTT_NOM: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_EFF_DRAM_RTT_NOM getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
+/// @param[out] uint8_t* memory to store the value
+/// @note Generated by gen_accessors.pl generateParameters (B)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  RTT_NOM value read to be programmed into MRS02 For RDIMMS, this is based off of
+/// the VPD For LRDIMMS, this comes from the
+/// SPD
+///
+inline fapi2::ReturnCode eff_dram_rtt_nom(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t* o_array)
+{
+    if (o_array == nullptr)
+    {
+        FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
+        return fapi2::FAPI2_RC_INVALID_PARAMETER;
+    }
+
+    uint8_t l_value[2][2][4];
+    auto l_mcs = i_target.getParent<fapi2::TARGET_TYPE_MCS>();
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DRAM_RTT_NOM, l_mcs, l_value) );
+    memcpy(o_array, &(l_value[mss::index(i_target)][0]), 8);
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_EFF_DRAM_RTT_NOM: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_EFF_DRAM_RTT_NOM getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
+/// @param[out] uint8_t* memory to store the value
+/// @note Generated by gen_accessors.pl generateParameters (C)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  RTT_NOM value read to be programmed into MRS02 For RDIMMS, this is based off of
+/// the VPD For LRDIMMS, this comes from the
+/// SPD
+///
+inline fapi2::ReturnCode eff_dram_rtt_nom(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
+{
+    if (o_array == nullptr)
+    {
+        FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
+        return fapi2::FAPI2_RC_INVALID_PARAMETER;
+    }
+
+    uint8_t l_value[2][2][4];
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DRAM_RTT_NOM, i_target, l_value) );
+    memcpy(o_array, &l_value, 16);
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_EFF_DRAM_RTT_NOM: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_EFF_DRAM_RTT_WR getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
+/// @param[out] uint8_t* memory to store the value
+/// @note Generated by gen_accessors.pl generateParameters (A)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  RTT_WR value read to be programmed into MRS02 For RDIMMS, this is based off of
+/// the VPD For LRDIMMS, this comes from the
+/// SPD
+///
+inline fapi2::ReturnCode eff_dram_rtt_wr(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t* o_array)
+{
+    if (o_array == nullptr)
+    {
+        FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
+        return fapi2::FAPI2_RC_INVALID_PARAMETER;
+    }
+
+    uint8_t l_value[2][2][4];
+    auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
+    auto l_mcs = l_mca.getParent<fapi2::TARGET_TYPE_MCS>();
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DRAM_RTT_WR, l_mcs, l_value) );
+    memcpy(o_array, &(l_value[mss::index(l_mca)][mss::index(i_target)][0]), 4);
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_EFF_DRAM_RTT_WR: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_EFF_DRAM_RTT_WR getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
+/// @param[out] uint8_t* memory to store the value
+/// @note Generated by gen_accessors.pl generateParameters (B)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  RTT_WR value read to be programmed into MRS02 For RDIMMS, this is based off of
+/// the VPD For LRDIMMS, this comes from the
+/// SPD
+///
+inline fapi2::ReturnCode eff_dram_rtt_wr(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t* o_array)
+{
+    if (o_array == nullptr)
+    {
+        FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
+        return fapi2::FAPI2_RC_INVALID_PARAMETER;
+    }
+
+    uint8_t l_value[2][2][4];
+    auto l_mcs = i_target.getParent<fapi2::TARGET_TYPE_MCS>();
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DRAM_RTT_WR, l_mcs, l_value) );
+    memcpy(o_array, &(l_value[mss::index(i_target)][0]), 8);
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_EFF_DRAM_RTT_WR: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_EFF_DRAM_RTT_WR getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
+/// @param[out] uint8_t* memory to store the value
+/// @note Generated by gen_accessors.pl generateParameters (C)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  RTT_WR value read to be programmed into MRS02 For RDIMMS, this is based off of
+/// the VPD For LRDIMMS, this comes from the
+/// SPD
+///
+inline fapi2::ReturnCode eff_dram_rtt_wr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
+{
+    if (o_array == nullptr)
+    {
+        FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
+        return fapi2::FAPI2_RC_INVALID_PARAMETER;
+    }
+
+    uint8_t l_value[2][2][4];
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DRAM_RTT_WR, i_target, l_value) );
+    memcpy(o_array, &l_value, 16);
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_EFF_DRAM_RTT_WR: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_EFF_DRAM_RTT_PARK getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
+/// @param[out] uint8_t* memory to store the value
+/// @note Generated by gen_accessors.pl generateParameters (A)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  RTT_PARK value read to be programmed into MRS05 For RDIMMS, this is based off of
+/// the VPD For LRDIMMS, this comes from the
+/// SPD
+///
+inline fapi2::ReturnCode eff_dram_rtt_park(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t* o_array)
+{
+    if (o_array == nullptr)
+    {
+        FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
+        return fapi2::FAPI2_RC_INVALID_PARAMETER;
+    }
+
+    uint8_t l_value[2][2][4];
+    auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
+    auto l_mcs = l_mca.getParent<fapi2::TARGET_TYPE_MCS>();
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DRAM_RTT_PARK, l_mcs, l_value) );
+    memcpy(o_array, &(l_value[mss::index(l_mca)][mss::index(i_target)][0]), 4);
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_EFF_DRAM_RTT_PARK: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_EFF_DRAM_RTT_PARK getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
+/// @param[out] uint8_t* memory to store the value
+/// @note Generated by gen_accessors.pl generateParameters (B)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  RTT_PARK value read to be programmed into MRS05 For RDIMMS, this is based off of
+/// the VPD For LRDIMMS, this comes from the
+/// SPD
+///
+inline fapi2::ReturnCode eff_dram_rtt_park(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t* o_array)
+{
+    if (o_array == nullptr)
+    {
+        FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
+        return fapi2::FAPI2_RC_INVALID_PARAMETER;
+    }
+
+    uint8_t l_value[2][2][4];
+    auto l_mcs = i_target.getParent<fapi2::TARGET_TYPE_MCS>();
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DRAM_RTT_PARK, l_mcs, l_value) );
+    memcpy(o_array, &(l_value[mss::index(i_target)][0]), 8);
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_EFF_DRAM_RTT_PARK: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_EFF_DRAM_RTT_PARK getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
+/// @param[out] uint8_t* memory to store the value
+/// @note Generated by gen_accessors.pl generateParameters (C)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  RTT_PARK value read to be programmed into MRS05 For RDIMMS, this is based off of
+/// the VPD For LRDIMMS, this comes from the
+/// SPD
+///
+inline fapi2::ReturnCode eff_dram_rtt_park(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
+{
+    if (o_array == nullptr)
+    {
+        FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
+        return fapi2::FAPI2_RC_INVALID_PARAMETER;
+    }
+
+    uint8_t l_value[2][2][4];
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DRAM_RTT_PARK, i_target, l_value) );
+    memcpy(o_array, &l_value, 16);
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_EFF_DRAM_RTT_PARK: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
 /// @brief ATTR_EFF_DIMM_DDR4_BC00 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
 /// @param[out] ref to the value uint8_t
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.C b/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.C
index 2e32427aa..9741df37b 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* Contributors Listed Below - COPYRIGHT 2016,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -836,7 +836,13 @@ fapi2::ReturnCode populate_decoder_caches( const fapi2::Target<TARGET_TYPE_DIMM>
     // Populate custom spd caches maps one dimm at a time
     o_factory_caches.emplace( std::make_pair( pos(i_target), i_pDecoder ) );
 
-    return fapi2::FAPI2_RC_SUCCESS;
+    // Populate some of the DIMM attributes early. This allows the following code to make
+    // decisions based on DIMM information. Expressly done after the factory has decided on the SPD version
+    FAPI_TRY( master_ranks_per_dimm_setter(i_target, i_pDecoder),
+              "%s. Failed master_ranks_per_dimm_setter()", mss::c_str(i_target) );
+
+fapi_try_exit:
+    return fapi2::current_err;
 }
 
 }// spd
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C
index 57f829f3b..02dc358d4 100644
--- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C
+++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -48,6 +48,9 @@
 #include <lib/utils/pos.H>
 #include <lib/utils/checker.H>
 #include <lib/utils/find.H>
+#include <lib/shared/mss_kind.H>
+#include <lib/utils/find.H>
+
 
 ///
 /// @brief Configure the attributes for each controller
@@ -75,7 +78,9 @@ fapi2::ReturnCode p9_mss_eff_config( const fapi2::Target<fapi2::TARGET_TYPE_MCS>
     for( const auto& l_dimm : mss::find_targets<fapi2::TARGET_TYPE_DIMM>(i_target) )
     {
         const auto l_dimm_pos = mss::pos(l_dimm);
-
+        uint8_t l_type = 0;
+        uint8_t l_gen = 0;
+        uint64_t l_kind = 0;
         // TODO RTC:152390 Create function to do map checking on cached values
         // Find decoder factory for this dimm position
         auto l_it = l_factory_caches.find(l_dimm_pos);
@@ -182,6 +187,31 @@ fapi2::ReturnCode p9_mss_eff_config( const fapi2::Target<fapi2::TARGET_TYPE_MCS>
         FAPI_TRY( l_eff_config.additive_latency(l_dimm) );
         FAPI_TRY( l_eff_config.data_mask(l_dimm) );
 
+        FAPI_TRY( mss::eff_dram_gen(l_dimm, l_gen) );
+        FAPI_TRY( mss::eff_dimm_type(l_dimm, l_type) );
+        l_kind = mss::dimm_kind (l_type, l_gen);
+
+        //One day we won't need this switch case, we can just specialize the methods via passed in target type
+        //Till then, we have a story
+        //TODO RTC: 166453
+        switch (l_kind)
+        {
+            case mss::KIND_LRDIMM_DDR4:
+                FAPI_TRY( l_eff_config.dram_rtt_nom<mss::KIND_LRDIMM_DDR4>(l_dimm) );
+                FAPI_TRY( l_eff_config.dram_rtt_wr<mss::KIND_LRDIMM_DDR4>(l_dimm) );
+                FAPI_TRY( l_eff_config.dram_rtt_park<mss::KIND_LRDIMM_DDR4>(l_dimm) );
+                break;
+
+            case mss::KIND_RDIMM_DDR4:
+                FAPI_TRY( l_eff_config.dram_rtt_nom<mss::KIND_RDIMM_DDR4>(l_dimm) );
+                FAPI_TRY( l_eff_config.dram_rtt_wr<mss::KIND_RDIMM_DDR4>(l_dimm) );
+                FAPI_TRY( l_eff_config.dram_rtt_park<mss::KIND_RDIMM_DDR4>(l_dimm) );
+                break;
+
+            default:
+                FAPI_ERR("Invalid DIMM type and or gen");
+                return fapi2::FAPI2_RC_INVALID_PARAMETER;
+        };
     }// dimm
 
     {