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authorBrian Silver <bsilver@us.ibm.com>2016-01-31 04:34:22 -0600
committerDaniel M. Crowell <dcrowell@us.ibm.com>2016-02-22 10:16:25 -0600
commit2bb27e8e132780b3eb96e9799223f53a30353cd5 (patch)
treeeea7ccdd14a246db2de7c8b9adab67f2058eb28e /src/import/chips/p9/procedures/hwp/memory
parent4b388bf1604d073c420e5047c96ccd16cdd6a2c1 (diff)
downloadtalos-hostboot-2bb27e8e132780b3eb96e9799223f53a30353cd5.tar.gz
talos-hostboot-2bb27e8e132780b3eb96e9799223f53a30353cd5.zip
Add dump_regs for PHY registers
Change-Id: I6357acba5d0563c8ef29291da264559f588a5b13 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/23810 Tested-by: Jenkins Server Reviewed-by: Andre A. Marin <aamarin@us.ibm.com> Reviewed-by: Craig C. Hamilton <cchamilt@us.ibm.com> Reviewed-by: Brian Silver <bsilver@us.ibm.com> Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/24532 Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory')
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C
index bfe6fa1b6..b0e72821c 100644
--- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C
+++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C
@@ -156,6 +156,8 @@ extern "C"
// • Section 5.2.6.2 WC Configuration 1 Register on page 436
// • Section 5.2.6.3 WC Configuration 2 Register on page 438
+ FAPI_TRY( mss::dump_regs<TARGET_TYPE_MCA>(p) );
+
// Get our rank pairs.
FAPI_TRY( mss::get_rank_pairs(p, l_pairs) );
@@ -177,8 +179,6 @@ extern "C"
FAPI_TRY( mss::dp16::reset_delay_values(p, l_pairs) );
}
- FAPI_TRY( mss::dump_cal_registers(p) );
-
FAPI_DBG("generating calibration CCS instructions: %d rank-pairs", l_pairs.size());
// For each rank pair we need to calibrate, pop a ccs instruction in an array and execute it.
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