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author | Alvin Wang <wangat@tw.ibm.com> | 2018-11-26 23:47:04 -0600 |
---|---|---|
committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2018-12-17 10:07:43 -0600 |
commit | 04cb76144aaec07ee499718989f482003a2a8879 (patch) | |
tree | 2944165cfe61b7645a13eb2e2a19274605aa5405 /src/import/chips/p9/procedures/hwp/memory | |
parent | d902dfa035625acb9007a7dc3e492737d63cee7a (diff) | |
download | talos-hostboot-04cb76144aaec07ee499718989f482003a2a8879.tar.gz talos-hostboot-04cb76144aaec07ee499718989f482003a2a8879.zip |
Moves fir reg to generic folder
Change-Id: Iff4e6449f97984f4d9853c40c39b082011112ec1
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69018
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69019
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory')
7 files changed, 16 insertions, 225 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/fir/fir.H b/src/import/chips/p9/procedures/hwp/memory/lib/fir/fir.H index 92fc8bd7e..30cee9392 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/fir/fir.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/fir/fir.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -39,22 +39,12 @@ #include <fapi2.H> #include <p9_mc_scom_addresses.H> #include <p9_mc_scom_addresses_fld.H> -#include <generic/memory/lib/utils/scom.H> +#include <generic/memory/lib/utils/fir/gen_mss_fir.H> +#include <generic/memory/lib/utils/shared/mss_generic_consts.H> namespace mss { -// -// Each FIR bit is contained in a register (set or unset) and is mapped to action and mask registers (defines -// their behavior). Likewise, each unit (MCBIST, MCS, MCA) has control bits defining whether the attentions -// from this unit represent special or host attentions. - -/// -/// @brief FIR Register Traits -/// @tparam R the FIR register -/// -template <uint64_t R > -struct firTraits; /// /// @brief FIR Register Traits for MCBISTFIR @@ -141,174 +131,6 @@ struct firTraits<MCA_MBACALFIRQ> static constexpr fapi2::TargetType T = fapi2::TARGET_TYPE_MCA; }; -namespace fir -{ - - -/// -/// @brief Small class to hold a FIR register -/// @tparam R the FIR register -/// @tparam RT the type traits for this register (derived) -/// -template< uint64_t R, typename RT = firTraits<R> > -class reg -{ - - private: - fapi2::Target<RT::T> iv_target; - - public: - - /// - /// @brief fir::reg constructor - /// @param[in] i_target representing the fapi2::Target used to scom register R - /// @param[out] a fapi2::ReturnCode indicating if the internal constructor opererations were a success - /// - reg( const fapi2::Target<RT::T>& i_target, fapi2::ReturnCode& o_rc ): - iv_target(i_target), - - // Fill our buffer with F's as we're going to clear the bits we want to - // unmask and then drop the result in to the _AND register. - iv_mask(~0) - { - // Priming Read - FAPI_TRY( mss::getScom(iv_target, RT::ACT0, iv_action0) ); - FAPI_TRY( mss::getScom(iv_target, RT::ACT1, iv_action1) ); - - fapi_try_exit: - o_rc = fapi2::current_err; - } - - /// - /// @brief Clear FIR bits - /// @tparam B the ordinial number of the bit in question - /// @return FAPI2_RC_SUCCESS iff ok - /// - template< uint64_t B > - inline fapi2::ReturnCode clear() const - { - fapi2::buffer<uint64_t> l_read; - FAPI_TRY( mss::getScom(iv_target, RT::REG, l_read) ); - l_read.clearBit<B>(); - FAPI_TRY( mss::putScom(iv_target, RT::REG, l_read) ); - - fapi_try_exit: - return fapi2::current_err; - } - /// - /// @brief Clear the entire register of FIR bits - /// @return FAPI2_RC_SUCCESS iff ok - /// - inline fapi2::ReturnCode clear() const - { - return mss::putScom(iv_target, RT::REG, 0); - } - - // Magic patterns in these functions are (Action0, Action1, Mask) - - /// - /// @brief Setup Checkstop (0,0,0) - /// @tparam B the ordinial number of the bit in question - /// @tparam C the bit count, defaults to 1 - /// @return fir::reg reference suitable for chaining - /// - template< uint64_t B, uint64_t C = 1 > - inline fir::reg<R>& checkstop() - { - return action_helper<B, C>(0, 0, 0); - } - - /// - /// @brief Setup Recoverable Error (0,1,0) - /// @tparam B the ordinial number of the bit in question - /// @tparam C the bit count, defaults to 1 - /// @return fir::reg reference sutable for chaining - /// - template< uint64_t B, uint64_t C = 1 > - inline fir::reg<R>& recoverable_error() - { - return action_helper<B, C>(0, 1, 0); - } - - /// - /// @brief Setup Attention (1,0,0) - /// @tparam B the ordinial number of the bit in question - /// @tparam C the bit count, defaults to 1 - /// @return fir::reg reference sutable for chaining - /// - template< uint64_t B, uint64_t C = 1 > - inline fir::reg<R>& attention() - { - return action_helper<B, C>(1, 0, 0); - // TK do we need to setup special attention or host attention here? - } - - /// - /// @brief Setup Local checkstop (1,1,0) - /// @tparam B the ordinial number of the bit in question - /// @tparam C the bit count, defaults to 1 - /// @return fir::reg reference sutable for chaining - /// - template< uint64_t B, uint64_t C = 1 > - inline fir::reg<R>& local_checkstop() - { - return action_helper<B, C>(1, 1, 0); - } - - /// - /// @brief Setup Masked (x,x,1) - /// @tparam B the ordinial number of the bit in question - /// @tparam C the bit count, defaults to 1 - /// @return fir::reg reference sutable for chaining - /// - template< uint64_t B, uint64_t C = 1 > - inline fir::reg<R>& masked() - { - return action_helper<B, C>(1, 1, 1); - } - - /// - /// @brief Write action0, action1 and mask for this register - /// @return fapi2::FAPI2_RC_SUCCESS iff ok - /// - inline fapi2::ReturnCode write() const - { - // Set action registers before unmasking to prevent unintended actions when you unmask. - FAPI_TRY( mss::putScom(iv_target, RT::ACT0, iv_action0) ); - FAPI_TRY( mss::putScom(iv_target, RT::ACT1, iv_action1) ); - FAPI_TRY( mss::putScom(iv_target, RT::MASK_AND, iv_mask) ); - - fapi_try_exit: - return fapi2::current_err; - } - - private: - - fapi2::buffer<uint64_t> iv_mask; - fapi2::buffer<uint64_t> iv_action0; - fapi2::buffer<uint64_t> iv_action1; - - /// - /// @brief Register helper takes a setting of bits for action0, action1 and mask and sets our internal state - /// @tparam B the fir bit ordinal number - /// @tparam C the bit count, defaults to 1 - /// @param[in] i_act0 the setting for action0 - /// @param[in] i_act1 the setting for action1 - /// @param[in] i_mask the setting for mask - /// @return reference to fir::reg, to be used for chaining - /// - template< uint64_t B, uint64_t C = 1 > - inline fir::reg<R>& action_helper(const uint64_t i_act0, const uint64_t i_act1, const uint64_t i_mask) - { - iv_mask.writeBit<B, C>(i_mask); - iv_action0.writeBit<B, C>(i_act0); - iv_action1.writeBit<B, C>(i_act1); - - return *this; - } -}; - -} } #endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/fir/unmask.C b/src/import/chips/p9/procedures/hwp/memory/lib/fir/unmask.C index 48845f53e..0e2cb2c93 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/fir/unmask.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/fir/unmask.C @@ -57,7 +57,7 @@ namespace unmask /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok /// template<> -fapi2::ReturnCode after_draminit_mc( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target ) +fapi2::ReturnCode after_draminit_mc<mss::mc_type::NIMBUS>( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target ) { FAPI_INF("unmask mss fir after draminit_mc"); @@ -121,7 +121,7 @@ fapi_try_exit: /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok /// template<> -fapi2::ReturnCode after_draminit_training( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target ) +fapi2::ReturnCode after_draminit_training<mss::mc_type::NIMBUS>( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target ) { FAPI_INF("unmask mss fir after draminit_training"); @@ -165,7 +165,7 @@ fapi_try_exit: /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok /// template<> -fapi2::ReturnCode after_scominit( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target ) +fapi2::ReturnCode after_scominit<mss::mc_type::NIMBUS>( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target ) { FAPI_INF("unmask (and clear) mss fir after scominit"); @@ -202,7 +202,7 @@ fapi_try_exit: /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok /// template<> -fapi2::ReturnCode after_phy_reset( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target ) +fapi2::ReturnCode after_phy_reset<mss::mc_type::NIMBUS>( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target ) { FAPI_INF("unmask mss fir after phy reset"); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/fir/unmask.H b/src/import/chips/p9/procedures/hwp/memory/lib/fir/unmask.H index 749eb50c3..7a4d271bc 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/fir/unmask.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/fir/unmask.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -37,6 +37,7 @@ #define _MSS_UNMASK_FIR_H_ #include <fapi2.H> +#include <generic/memory/lib/utils/fir/gen_mss_unmask.H> namespace mss { @@ -44,41 +45,6 @@ namespace mss namespace unmask { -/// -/// @brief Unmask and setup actions performed after draminit_mc -/// @tparam T the fapi2::TargetType which hold the FIR bits -/// @param[in] i_target the fapi2::Target -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok -/// -template< fapi2::TargetType T > -fapi2::ReturnCode after_draminit_mc( const fapi2::Target<T>& i_target ); - -/// -/// @brief Unmask and setup actions performed after draminit_training -/// @tparam T the fapi2::TargetType which hold the FIR bits -/// @param[in] i_target the fapi2::Target -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok -/// -template< fapi2::TargetType T > -fapi2::ReturnCode after_draminit_training( const fapi2::Target<T>& i_target ); - -/// -/// @brief Unmask and setup actions performed after mss_scominit -/// @tparam T the fapi2::TargetType which hold the FIR bits -/// @param[in] i_target the fapi2::Target of the MCBIST -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok -/// -template< fapi2::TargetType T > -fapi2::ReturnCode after_scominit( const fapi2::Target<T>& i_target ); - -/// -/// @brief Unmask and setup actions performed after mss_ddr_phy_reset -/// @tparam T the fapi2::TargetType which hold the FIR bits -/// @param[in] i_target the fapi2::Target of the MCBIST -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok -/// -template< fapi2::TargetType T > -fapi2::ReturnCode after_phy_reset( const fapi2::Target<T>& i_target ); } diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C index be66a83fb..27b616a72 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C @@ -198,7 +198,8 @@ extern "C" // The algorithm is 'good path do after_phy_reset, all paths (error or not) perform the checks // which are defined in during_phy_reset'. We won't run after_phy_reset (unmask of FIR) unless // we're done with a success. - FAPI_TRY( mss::unmask::after_phy_reset(i_target), "%s Error in p9_mss_ddr_phy_reset.C", mss::c_str(i_target) ); + FAPI_TRY( mss::unmask::after_phy_reset<mss::mc_type::NIMBUS>(i_target), "%s Error in p9_mss_ddr_phy_reset.C", + mss::c_str(i_target) ); // Leave as we're all good and checked the FIR already ... return fapi2::current_err; diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C index f1e42ffb5..18a0c2160 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C @@ -146,7 +146,8 @@ extern "C" } // At this point the DDR interface must be monitored for memory errors. Memory related FIRs should be unmasked. - FAPI_TRY( mss::unmask::after_draminit_mc(i_target), "%s Failed after_draminit_mc", mss::c_str(i_target) ); + FAPI_TRY( mss::unmask::after_draminit_mc<mss::mc_type::NIMBUS>(i_target), "%s Failed after_draminit_mc", + mss::c_str(i_target) ); fapi_try_exit: FAPI_INF("End draminit MC"); diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C index 45d8cbcd5..da65aaf12 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C @@ -212,7 +212,7 @@ extern "C" // We do it here in order to train every port FAPI_TRY( mss::draminit_training_error_handler(l_fails) ); // Unmask FIR - FAPI_TRY( mss::unmask::after_draminit_training(i_target), "Error in p9_mss_draminit" ); + FAPI_TRY( mss::unmask::after_draminit_training<mss::mc_type::NIMBUS>(i_target), "Error in p9_mss_draminit" ); fapi_try_exit: FAPI_INF("End draminit training"); diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_scominit.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_scominit.C index 3282d6fe3..e8acb8237 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_scominit.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_scominit.C @@ -117,7 +117,8 @@ fapi2::ReturnCode p9_mss_scominit( const fapi2::Target<TARGET_TYPE_MCBIST>& i_ta FAPI_TRY( mss::phy_scominit(i_target), "%s failed phy_scominit", mss::c_str(i_target) ); // Do FIRry things - FAPI_TRY( mss::unmask::after_scominit(i_target), "%s failed after_scominit", mss::c_str(i_target) ); + FAPI_TRY( mss::unmask::after_scominit<mss::mc_type::NIMBUS>(i_target), "%s failed after_scominit", + mss::c_str(i_target) ); fapi_try_exit: FAPI_INF("%s End MSS SCOM init ReturnCode:0x%016lx", mss::c_str(i_target), uint64_t(fapi2::current_err)); |