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| author | Brian Silver <bsilver@us.ibm.com> | 2016-02-24 10:11:33 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-03-02 16:22:30 -0500 |
| commit | d8f5f105b717836ceb98a29951a599b88603a5b6 (patch) | |
| tree | 9ee661ec7f22efe8bb70ddd8a2c15db1dffc1f40 /src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C | |
| parent | 1deded54528a9ad6483d4cc5d1540facdf8dde2c (diff) | |
| download | talos-hostboot-d8f5f105b717836ceb98a29951a599b88603a5b6.tar.gz talos-hostboot-d8f5f105b717836ceb98a29951a599b88603a5b6.zip | |
Change WC to follow the new register block pattern
Change-Id: I20f22cb5ea50c7f8e0d53bb39ef452f892187d2a
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/20851
Tested-by: Jenkins Server
Tested-by: Auto Mirror
Tested-by: Hostboot CI
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: CRAIG C. HAMILTON <cchamilt@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/20815
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C index b0e72821c..c2217182b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C @@ -134,13 +134,6 @@ extern "C" FAPI_TRY( mss::putScom(p, MCA_DDRPHY_PC_INIT_CAL_ERROR_P0, 0) ); FAPI_TRY( mss::putScom(p, MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0, 0) ); - // Hit the reset button for wr_lvl values. These won't reset until the next run of wr_lvl - FAPI_TRY( mss::reset_wc_config0(p) ); - FAPI_TRY( mss::reset_wc_config1(p) ); - FAPI_TRY( mss::reset_wc_config2(p) ); - - FAPI_TRY( mss::reset_wc_rtt_wr_swap_enable(p) ); - // The following registers must be configured to the correct operating environment: // Unclear, can probably be 0's for sim BRS |
