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| author | Brian Silver <bsilver@us.ibm.com> | 2016-09-02 12:04:30 -0500 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2016-09-12 13:51:52 -0400 |
| commit | 4a6f519abeba64bdc33d15bc97b07e54471609d1 (patch) | |
| tree | b20b65269ec4d74198ad61b6b277a26b38630577 /src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C | |
| parent | 0f29aac88c66f0e5c36756b8fdafe2bf2fbd3dd1 (diff) | |
| download | talos-hostboot-4a6f519abeba64bdc33d15bc97b07e54471609d1.tar.gz talos-hostboot-4a6f519abeba64bdc33d15bc97b07e54471609d1.zip | |
Change SEQ timings, SEQ ODT, WC config and DQS polarity
SEQ timings make use of new timing functions
SEQ ODT changes VBU VPD, makes sure ZZ VPD is correct
WC Config makes cal big step 8/128th
Add Monza DQS polarity workarounds
Change-Id: I1b2059188616674f885253492cba7350d268214f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29219
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29221
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C index e1c67caf6..23546af61 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C @@ -124,12 +124,7 @@ extern "C" // The following registers must be configured to the correct operating environment: - // Unclear, can probably be 0's for sim BRS // • Section 5.2.5.10 SEQ ODT Write Configuration {0-3} on page 422 - - FAPI_TRY( mss::reset_seq_config0(p) ); - FAPI_TRY( mss::reset_seq_rd_wr_data(p) ); - FAPI_TRY( mss::reset_odt_config(p) ); // These are reset in phy_scominit |
