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authorBrian Silver <bsilver@us.ibm.com>2016-02-23 13:06:24 -0600
committerDaniel M. Crowell <dcrowell@us.ibm.com>2016-04-01 21:24:12 -0400
commit63c0bd93248e3f5e4f71f8beb421bc1dda22d660 (patch)
treee64896126fc993252dceb65b3ace363a457fe865 /src/import/chips/p9/procedures/hwp/memory/lib
parent7579370f3bac7777f3b509aa2f33b6612bf44ff3 (diff)
downloadtalos-hostboot-63c0bd93248e3f5e4f71f8beb421bc1dda22d660.tar.gz
talos-hostboot-63c0bd93248e3f5e4f71f8beb421bc1dda22d660.zip
Change read control API to match desired design, add design doc
Change-Id: I008392a4b24461906735546b9af37a89c5600600 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/24657 Tested-by: Jenkins Server Reviewed-by: Craig C. Hamilton <cchamilt@us.ibm.com> Reviewed-by: Andre A. Marin <aamarin@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22771 Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib')
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C12
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H31
2 files changed, 32 insertions, 11 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
index 79b0c9d8b..36e8f13c7 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
@@ -885,13 +885,7 @@ fapi2::ReturnCode phy_scominit(const fapi2::Target<TARGET_TYPE_MCBIST>& i_target
FAPI_TRY( mss::dp16::read_clock_enable(p, l_pairs) );
// Read Control reset
- FAPI_TRY( mss::rc<TARGET_TYPE_MCA>::reset_config0(p) );
- FAPI_TRY( mss::rc<TARGET_TYPE_MCA>::reset_config1(p) );
- FAPI_TRY( mss::rc<TARGET_TYPE_MCA>::reset_config2(p) );
- FAPI_TRY( mss::rc<TARGET_TYPE_MCA>::reset_config3(p) );
-
- FAPI_TRY( mss::rc<TARGET_TYPE_MCA>::reset_vref_config0(p) );
- FAPI_TRY( mss::rc<TARGET_TYPE_MCA>::reset_vref_config1(p) );
+ FAPI_TRY( mss::rc::reset(p) );
}
fapi_try_exit:
@@ -959,14 +953,14 @@ inline fapi2::ReturnCode setup_cal_config( const fapi2::Target<fapi2::TARGET_TYP
// If READ_CNTR == 0 && READ_CTR_2D_VREF == 1, CALIBRATION_ENABLE = 1 and SKIP = 1
// If READ_CNTR == 1 && READ_CTR_2D_VREF == 0, CALIBRATION_ENABLE = 0 and SKIP = don't care
// If READ_CNTR == 0 && READ_CTR_2D_VREF == 0, CALIBRATION_ENABLE = 0 and SKIP = don't care
- FAPI_TRY( mss::rc<TARGET_TYPE_MCA>::read_vref_config1(i_target, l_data) );
+ FAPI_TRY( mss::rc::read_vref_config1(i_target, l_data) );
l_data.writeBit<MCA_DDRPHY_RC_RDVREF_CONFIG1_P0_CALIBRATION_ENABLE>(
i_cal_steps_enabled.getBit<WRITE_CTR_2D_VREF>());
l_data.writeBit<MCA_DDRPHY_RC_RDVREF_CONFIG1_P0_SKIP_RDCENTERING>(
! i_cal_steps_enabled.getBit<WRITE_CTR>());
- FAPI_TRY( mss::rc<TARGET_TYPE_MCA>::write_vref_config1(i_target, l_data) );
+ FAPI_TRY( mss::rc::write_vref_config1(i_target, l_data) );
}
// Write Centering
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H
index 59e7a2ce5..9c9eb82b0 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H
@@ -126,8 +126,8 @@ class rcTraits<fapi2::TARGET_TYPE_MCA>
/// @tparam T fapi2 Target Type - derived
/// @tparam TT traits type defaults to rcTraits<T>
///
-template< fapi2::TargetType T, typename TT = rcTraits<T> >
-class rc
+template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = rcTraits<T> >
+class rc_class
{
public:
@@ -140,6 +140,7 @@ class rc
static inline fapi2::ReturnCode read_vref_config0( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
{
FAPI_TRY( mss::getScom(i_target, TT::RC_VREF_CONFIG0_REG, o_data) );
+ FAPI_DBG("rc_vref_config0: 0x%016llx", o_data);
fapi_try_exit:
return fapi2::current_err;
}
@@ -168,6 +169,7 @@ class rc
static inline fapi2::ReturnCode read_vref_config1( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
{
FAPI_TRY( mss::getScom(i_target, TT::RC_VREF_CONFIG1_REG, o_data) );
+ FAPI_DBG("rc_vref_config1: 0x%016llx", o_data);
fapi_try_exit:
return fapi2::current_err;
}
@@ -197,6 +199,7 @@ class rc
static inline fapi2::ReturnCode read_config0( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
{
FAPI_TRY( mss::getScom(i_target, TT::RC_CONFIG0_REG, o_data) );
+ FAPI_DBG("rc_config0: 0x%016llx", o_data);
fapi_try_exit:
return fapi2::current_err;
}
@@ -225,6 +228,7 @@ class rc
static inline fapi2::ReturnCode read_config1( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
{
FAPI_TRY( mss::getScom(i_target, TT::RC_CONFIG1_REG, o_data) );
+ FAPI_DBG("rc_config1: 0x%016llx", o_data);
fapi_try_exit:
return fapi2::current_err;
}
@@ -252,6 +256,7 @@ class rc
static inline fapi2::ReturnCode read_config2( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
{
FAPI_TRY( mss::getScom(i_target, TT::RC_CONFIG2_REG, o_data) );
+ FAPI_DBG("rc_config2: 0x%016llx", o_data);
fapi_try_exit:
return fapi2::current_err;
}
@@ -279,6 +284,7 @@ class rc
static inline fapi2::ReturnCode read_config3( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
{
FAPI_TRY( mss::getScom(i_target, TT::RC_CONFIG3_REG, o_data) );
+ FAPI_DBG("rc_config3: 0x%016llx", o_data);
fapi_try_exit:
return fapi2::current_err;
}
@@ -452,8 +458,29 @@ class rc
return fapi2::current_err;
}
+ ///
+ /// @brief reset rc
+ /// @param[in] i_target fapi2 target of the port
+ /// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS if ok
+ ///
+ static inline fapi2::ReturnCode reset( const fapi2::Target<T>& i_target )
+ {
+ FAPI_TRY( reset_config0(i_target) );
+ FAPI_TRY( reset_config1(i_target) );
+ FAPI_TRY( reset_config2(i_target) );
+ FAPI_TRY( reset_config3(i_target) );
+
+ FAPI_TRY( reset_vref_config0(i_target) );
+ FAPI_TRY( reset_vref_config1(i_target) );
+
+ fapi_try_exit:
+ return fapi2::current_err;
+ }
+
};
+using rc = rc_class<fapi2::TARGET_TYPE_MCA>;
+
}
#endif
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