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| author | Jacob Harvey <jlharvey@us.ibm.com> | 2017-05-25 16:47:28 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-06-07 16:40:49 -0400 |
| commit | c09c9035a23e945413b38535bba72ba2331ab526 (patch) | |
| tree | a54642d43aa77ef18f0e21f5567eceab722cef78 /src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dqs_align_workarounds.H | |
| parent | 415f2d43ab2076c790670e69f7e3393878fc612d (diff) | |
| download | talos-hostboot-c09c9035a23e945413b38535bba72ba2331ab526.tar.gz talos-hostboot-c09c9035a23e945413b38535bba72ba2331ab526.zip | |
Turn off PHY refresh for RD_CNTR - RD_VREF
Change-Id: Id7ca905dc984fdf1cd8070ffd55ed08031522f45
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41049
Dev-Ready: JACOB L. HARVEY <jlharvey@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41058
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dqs_align_workarounds.H')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dqs_align_workarounds.H | 18 |
1 files changed, 15 insertions, 3 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dqs_align_workarounds.H b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dqs_align_workarounds.H index 52ec94fcf..d38f55d30 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dqs_align_workarounds.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dqs_align_workarounds.H @@ -27,8 +27,6 @@ #define _MSS_WORKAROUNDS_DQS_ALIGN #include <fapi2.H> -#include <p9_mc_scom_addresses.H> -#include <mss_attribute_accessors.H> namespace mss { @@ -54,11 +52,25 @@ fapi2::ReturnCode set_timing0_trfc(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& fapi2::ReturnCode set_init_cal_refresh(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target); /// +/// @brief Clear the PHY sequencer refresh +/// @param[in] i_target the fapi2 target of the port +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +fapi2::ReturnCode clear_init_cal_refresh(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target); + +/// /// @brief Set PHY sequencer to trigger refresh during init cal /// @param[in] i_target the fapi2 target of the port /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok /// -fapi2::ReturnCode refresh(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target); +fapi2::ReturnCode turn_on_refresh(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target); + +/// +/// @brief Turn off refresh after dqs training has been run +/// @param[in] i_target the fapi2 target of the port +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +fapi2::ReturnCode turn_off_refresh(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target); }// dqs_align }// workarounds |
