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| author | Andre Marin <aamarin@us.ibm.com> | 2016-04-19 20:15:17 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-05-12 11:10:06 -0400 |
| commit | 26753f805150fca2ada15f8527b4433a7a4edaa0 (patch) | |
| tree | 9cbec57bd369c16a21f4deee8223ccb203d0663b /src/import/chips/p9/procedures/hwp/memory/lib/spd | |
| parent | effcd0c0d34e5e4032324e57a4d6d8d881167e32 (diff) | |
| download | talos-hostboot-26753f805150fca2ada15f8527b4433a7a4edaa0.tar.gz talos-hostboot-26753f805150fca2ada15f8527b4433a7a4edaa0.zip | |
Fix throttle procedure & MSS attribute clean up
Change-Id: Iccebe2f5bbad9d4fed2de914e0b65dba0b0b4662
Original-Change-Id: I7b545b65aaf9cdfea08ab2c5142898f5c971a74b
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23486
Tested-by: Jenkins Server
Tested-by: Hostboot CI
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24407
Tested-by: FSP CI Jenkins
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/spd')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_decoder.H | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_decoder.H b/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_decoder.H index 6f983686b..df1979547 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_decoder.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_decoder.H @@ -851,8 +851,8 @@ class decoder /// integer and the Fine Offset for tRCmin (SPD byte 120) /// used for correction to get the actual value. /// - virtual fapi2::ReturnCode min_active_to_active_refresh_delay_time(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& - i_target, + virtual + fapi2::ReturnCode min_active_to_active_refresh_delay_time(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, int64_t& o_value); /// /// @brief Decodes SDRAM Minimum Refresh Recovery Delay Time 1 |
