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| author | Stephen Glancy <sglancy@us.ibm.com> | 2018-09-27 09:53:41 -0500 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2018-10-03 10:53:59 -0500 |
| commit | a4e14b209192f4f0b66493c93f7077e61cbe0516 (patch) | |
| tree | 9a4b60ae84ea6b7edd52d07ddcff83a0481a25ed /src/import/chips/p9/procedures/hwp/memory/lib/shared | |
| parent | 6d61a393a74b94c0e6bf206c43353181bff8b69d (diff) | |
| download | talos-hostboot-a4e14b209192f4f0b66493c93f7077e61cbe0516.tar.gz talos-hostboot-a4e14b209192f4f0b66493c93f7077e61cbe0516.zip | |
Adds per-Buffer addressability API for LRDIMM
Change-Id: I600dd1fe8b9595d2bc0041e7fc2c009c2477d0e3
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66727
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66759
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/shared')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H index bbd083730..56dd35339 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H @@ -67,6 +67,7 @@ enum sizes MAX_DQ_NIBBLES = MAX_DQ_BITS / BITS_PER_NIBBLE, ///< For ISDIMMs are 18 DQ nibbles for DQ 72 bits MAX_DRAMS_X8 = MAX_DQ_BITS / BITS_PER_BYTE, ///< For x8's there are 9 DRAM for 72 bits MAX_DRAMS_X4 = MAX_DQ_BITS / BITS_PER_NIBBLE, ///< For x4's there are 18 DRAM for 72 bits + MAX_LRDIMM_BUFFERS = MAX_DRAMS_X8, NUM_MRW_FREQS = 4, ///< Used for ATTR_MSS_MRW_SUPPORTED_FREQ @@ -200,6 +201,10 @@ enum ffdc_function_codes // CW engine information CW_DATA_ENGINE = 117, CW_INFO_ENGINE = 118, + + // PBA function codes + PBA_EXECUTE_CONTAINER = 80, + PBA_EXECUTE_VECTOR = 81, }; enum states |
