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| author | Brian Silver <bsilver@us.ibm.com> | 2016-09-21 13:55:25 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-09-25 13:25:06 -0400 |
| commit | 97de3f088e7509bd8ff05712f4936716d732a3bd (patch) | |
| tree | ab92e12c64091602f3cad4224ac921ae952879ab /src/import/chips/p9/procedures/hwp/memory/lib/shared | |
| parent | ac77052e578c98e32754d6f9120890c29ea023da (diff) | |
| download | talos-hostboot-97de3f088e7509bd8ff05712f4936716d732a3bd.tar.gz talos-hostboot-97de3f088e7509bd8ff05712f4936716d732a3bd.zip | |
Change WR_CNTR_FW values
Add unit test for cal timers
Change-Id: I4b5283fda50677c9935dff0e1f499a008ed2c5ca
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30092
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30093
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/shared')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H index 7477f683d..15b71222c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H @@ -68,12 +68,6 @@ enum sizes WR_LVL_PRE_DLY = 0b101010, WR_LVL_NUM_VALID_SAMPLES = 0x5, - // THIS IS LIKELY INCORRECT - Should be defined in the DDR4 write centering protocol BRS - // This field must be set to the larger of the two values in number of memory clock cycles. - // FW_RD_WR = max(tWTR + 11, AL + tRTP + 3) - WR_CNTR_FW_RD_WR = 0x11 + 4, - WR_CNTR_FW_WR_RD = 0x0, - // Attribute? BRS COARSE_CAL_STEP_SIZE = 0x4, CONSEQ_PASS = 0x8, |
