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authorBrian Silver <bsilver@us.ibm.com>2016-04-05 14:43:41 -0500
committerDaniel M. Crowell <dcrowell@us.ibm.com>2016-04-25 13:45:00 -0400
commit84245de79e62f285cd4bd3201dcf8ec8c92d1f42 (patch)
tree6b8e5de5183fd98f90875631798d1c68bcfae3a8 /src/import/chips/p9/procedures/hwp/memory/lib/shared
parent6d41c4bef52f59d6363d813d6b2b3b8a0d4f828c (diff)
downloadtalos-hostboot-84245de79e62f285cd4bd3201dcf8ec8c92d1f42.tar.gz
talos-hostboot-84245de79e62f285cd4bd3201dcf8ec8c92d1f42.zip
Add L2 p9_mss_scrub
Change inversion so in sim we run with inversion off Change address counting mode to be disabled by default Remove ATTR_MCBIST attributes Change-Id: I233851de5186e053df0b5a4b25eee42763b35755 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22914 Tested-by: Jenkins Server Tested-by: Hostboot CI Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22917 Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/shared')
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H
index cf2c5a142..569461574 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H
@@ -80,6 +80,7 @@ enum times
DELAY_100NS = 100, ///< general purpose 100 ns delay for HW mode
DELAY_1US = 1000, ///< general purpose 1 usec delay for HW mode
DELAY_100US = 100000, ///< general purpose 100 usec delay for HW mode
+ DELAY_1MS = 1000000, ///< general purpose 1 ms delay for HW mode
// From the DDR4spec 2400 speed - need to be changed to read attributes. BRS
tWLO = 10,
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