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| author | Jacob Harvey <jlharvey@us.ibm.com> | 2017-09-19 09:57:54 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-09-26 17:08:55 -0400 |
| commit | 7f59b42ea81b713c5e3c0cbeed38bd8858aa3ff6 (patch) | |
| tree | ebd9218a76a6f078d5088b850850c161de093d5c /src/import/chips/p9/procedures/hwp/memory/lib/shared | |
| parent | ad079f548f91b86b0526927ff32659e82349f895 (diff) | |
| download | talos-hostboot-7f59b42ea81b713c5e3c0cbeed38bd8858aa3ff6.tar.gz talos-hostboot-7f59b42ea81b713c5e3c0cbeed38bd8858aa3ff6.zip | |
Increment red_waterfall for low vdn fix
Change-Id: Iaa5dbf94fe223cdfef7ebbfe8598f98f5472c956
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46420
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Dev-Ready: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46455
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/shared')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H index 47e36b170..cf6a871e5 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H @@ -232,7 +232,7 @@ enum cal_steps : uint64_t INITIAL_PAT_WR_TO_RD_CTR_LEN = inclusive_range(INITIAL_PAT_WR, READ_CTR), WR_VREF_TO_COARSE_RD_LEN = inclusive_range(WRITE_CTR_2D_VREF, COARSE_RD), - RDCLK_ALIGN_TO_RD_CTR_LEN = inclusive_range(RDCLK_ALIGN, READ_CTR), + READ_VREF_TO_READ_CTR_LEN = inclusive_range(READ_CTR_2D_VREF, READ_CTR), // In this case, we just want to clear everything prior to WR 2D VREF, inclusive range also kills the WR VREF bit DRAM_ZQCAL_UP_TO_WRITE_CTR_2D_VREF = WRITE_CTR_2D_VREF, }; |
