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| author | Stephen Glancy <sglancy@us.ibm.com> | 2017-11-28 14:28:49 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-01-13 14:14:56 -0500 |
| commit | 6650adcec6acc4358ded7a9e2256d096123fde8b (patch) | |
| tree | 95f990074d815ef71eb2b4dc9211decc6051459f /src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H | |
| parent | 21407ef5012141424473c7df5839dc4ab9ab662a (diff) | |
| download | talos-hostboot-6650adcec6acc4358ded7a9e2256d096123fde8b.tar.gz talos-hostboot-6650adcec6acc4358ded7a9e2256d096123fde8b.zip | |
Updates training advanced and adds custom WR CTR
Breaks apart and reorganizes training advanced code
Adds custom pattern WR CTR in training advanced
Updates custom WR/RD patterns for characterization data
Change-Id: I3fc6e515f0ae2f853ce53a198a82b7513da4eea5
CQ:SW411492
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50118
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50141
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H index 4aa8db4cf..1958501e3 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H @@ -251,11 +251,12 @@ enum cal_steps : uint64_t WRITE_CTR = 17, ///< Write Centering COARSE_WR = 18, ///< Initial Coarse Pattern Write COARSE_RD = 19, ///< Coarse Read Centering - TRAINING_ADV = 20, ///< Flag for draminit training advance in the attribute/ CUSTOM_READ_CTR in code + TRAINING_ADV_RD = 20, ///< Flag for draminit training advance in the attribute/ CUSTOM_READ_CTR in code + TRAINING_ADV_WR = 21, ///< Flag for draminit training advance in the attribute/ CUSTOM_WRITE_CTR in code // Not *exactly* a cal step but go w/it - RUN_ALL_CAL_STEPS = 0xFFFFF800, - RUN_CAL_SKIP_WR_RD_2D_VREF = 0xFFFD7800, + RUN_ALL_CAL_STEPS = 0xFFFFFC00, + RUN_CAL_SKIP_WR_RD_2D_VREF = 0xFFFD7C00, INITIAL_PAT_WR_TO_RD_CTR_LEN = inclusive_range(INITIAL_PAT_WR, READ_CTR), WR_VREF_TO_COARSE_RD_LEN = inclusive_range(WRITE_CTR_2D_VREF, COARSE_RD), |
