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| author | Stephen Glancy <sglancy@us.ibm.com> | 2018-08-17 14:42:26 -0500 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2018-09-18 10:43:41 -0500 |
| commit | 444aeb467542541afb6aa8072037c8ddc74ab10c (patch) | |
| tree | 1c4ca88630d0c69709cb16c4da3fd98d1d69f610 /src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H | |
| parent | 4f35730b3dbecc04c63c2cd6a269eba2bc19fe33 (diff) | |
| download | talos-hostboot-444aeb467542541afb6aa8072037c8ddc74ab10c.tar.gz talos-hostboot-444aeb467542541afb6aa8072037c8ddc74ab10c.zip | |
Adds skeleton code for LRDIMM
Change-Id: I3f55896a48347fff7152c3a2a68cf8fab4fa0689
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64813
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64967
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H index c05d1cb8e..04c84f68c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H @@ -234,6 +234,7 @@ enum states // These are bit positions. 0 is the left most bit. enum cal_steps : uint64_t { + // TK:LRDIMM Update calibration steps to add or remove LRDIMM steps DRAM_ZQCAL = 0, ///< DRAM ZQ Calibration Long DB_ZQCAL = 1, ///< (LRDIMM) Data Buffer ZQ Calibration Long MREP = 2, ///< (LRDIMM) DRAM Interface MDQ Receive Enable Phase @@ -257,6 +258,7 @@ enum cal_steps : uint64_t TRAINING_ADV_RD = 20, ///< Flag for draminit training advance in the attribute/ CUSTOM_READ_CTR in code TRAINING_ADV_WR = 21, ///< Flag for draminit training advance in the attribute/ CUSTOM_WRITE_CTR in code + // TK:LRDIMM Update total calibration steps to have "LRDIMM" specific ones here // Not *exactly* a cal step but go w/it RUN_ALL_CAL_STEPS = 0xFFFFFC00, RUN_CAL_SKIP_WR_RD_2D_VREF = 0xFFFD7C00, |
