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| author | Stephen Glancy <sglancy@us.ibm.com> | 2017-09-21 10:14:04 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-10-02 23:45:51 -0400 |
| commit | 3890040afa1dc93d58476d68df35cb44d49c57b2 (patch) | |
| tree | 1c1538e4b8bb40a8a9d65bc8e900a84bb2caa586 /src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H | |
| parent | f21a18e501c28d932ee24f11a7a3ffaa93228735 (diff) | |
| download | talos-hostboot-3890040afa1dc93d58476d68df35cb44d49c57b2.tar.gz talos-hostboot-3890040afa1dc93d58476d68df35cb44d49c57b2.zip | |
Updates error paths for PRD FIR checking
FIR's could cause errors within hardware procedures. PRD has
the capability to retrigger a procedure if it sees an error.
We might be able to avoid IPL issues with this, so if a FIR
has been hit during hardware enabled code (CCS or calibration),
then log the error and let PRD find the "new" FIR that could have
caused the hardware engine to have an issue. If there is some other
problem, the retriggered HWP will find it.
Change-Id: I81599d1d0c4b4c256b79820b4a7e2eafc09e206b
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46571
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46584
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H index cf6a871e5..d6e5c4f53 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H @@ -199,6 +199,7 @@ enum ffdc_functions RD_CTR_WORKAROUND_READ_DATA = 7, OVERRIDE_ODT_WR_CONFIG = 8, RECORD_BAD_BITS_HELPER = 9, + SET_PAIR_VALID = 10, }; // Static consts describing the bits used in the cal_step_enable attribute // These are bit positions. 0 is the left most bit. |
