diff options
| author | Stephen Glancy <sglancy@us.ibm.com> | 2017-11-28 14:28:49 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-01-13 14:14:56 -0500 |
| commit | 6650adcec6acc4358ded7a9e2256d096123fde8b (patch) | |
| tree | 95f990074d815ef71eb2b4dc9211decc6051459f /src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H | |
| parent | 21407ef5012141424473c7df5839dc4ab9ab662a (diff) | |
| download | talos-hostboot-6650adcec6acc4358ded7a9e2256d096123fde8b.tar.gz talos-hostboot-6650adcec6acc4358ded7a9e2256d096123fde8b.zip | |
Updates training advanced and adds custom WR CTR
Breaks apart and reorganizes training advanced code
Adds custom pattern WR CTR in training advanced
Updates custom WR/RD patterns for characterization data
Change-Id: I3fc6e515f0ae2f853ce53a198a82b7513da4eea5
CQ:SW411492
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50118
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50141
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H | 45 |
1 files changed, 44 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H index e36b5969a..40924bc20 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H @@ -184,6 +184,9 @@ class dp16Traits<fapi2::TARGET_TYPE_MCA> static const std::vector<std::vector<std::pair<uint64_t, uint64_t>>> BIT_DISABLE_REG; + // WR delay register + static const std::vector<std::vector<uint64_t>> WR_DELAY_REG; + // WR VREF registers static const std::vector< uint64_t > WR_VREF_CONFIG0_REG; static const std::vector< uint64_t > WR_VREF_CONFIG1_REG; @@ -452,7 +455,7 @@ class rd_ctr_settings /// @brief Restore settings for a given rank pair /// @return FAPI2_RC_SUCCES iff ok /// - fapi2::ReturnCode restore(); + fapi2::ReturnCode restore() const; private: const fapi2::Target<T> iv_target; @@ -464,6 +467,46 @@ class rd_ctr_settings }; /// +/// @class wr_ctr_settings +/// @brief Stores pre-training_adv WR_CTR PHY settings, so they can be restored if training_adv fails +/// @tparam T target type representing a port +/// +template< fapi2::TargetType T > +class wr_ctr_settings +{ + public: + wr_ctr_settings() = delete; + + /// + /// @brief rd_ctr_settings constructor + /// @param[in] i_target the port target + /// @param[in] i_rp the rank pair + /// + wr_ctr_settings( const fapi2::Target<T>& i_target, const uint64_t i_rp ): + iv_target(i_target), iv_rp(i_rp) + { + } + + /// + /// @brief Save settings for a given rank pair + /// @return FAPI2_RC_SUCCES iff ok + /// + fapi2::ReturnCode save(); + + /// + /// @brief Restore settings for a given rank pair + /// @return FAPI2_RC_SUCCES iff ok + /// + fapi2::ReturnCode restore() const; + + private: + const fapi2::Target<T> iv_target; + const uint64_t iv_rp; + std::vector<fapi2::buffer<uint64_t>> iv_write_delay; + std::vector<std::pair<fapi2::buffer<uint64_t>, fapi2::buffer<uint64_t> > > iv_dq_disable; +}; + +/// /// @brief Read TSYS_DATA /// @tparam I DP16 instance /// @tparam T fapi2 Target Type - derived |
