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| author | Matthew Hickman <Matthew.Hickman@ibm.com> | 2019-04-15 16:32:46 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2019-05-13 10:46:41 -0500 |
| commit | 2b3c06d520853a436ac78050482168752dcd6efd (patch) | |
| tree | 468501e635d138c36c7ba9265a80de9f29093730 /src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C | |
| parent | d893f5ac1b3d25eb3bf7799bb601afe8406c7cbc (diff) | |
| download | talos-hostboot-2b3c06d520853a436ac78050482168752dcd6efd.tar.gz talos-hostboot-2b3c06d520853a436ac78050482168752dcd6efd.zip | |
Fixed the ccs port merge conflicts and added lab code
Change-Id: I665ea2460a5ace289b17ae868b07a8876b65a0c8
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75236
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76885
Reviewed-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C index 792e89fb2..40c6ac292 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C @@ -48,6 +48,7 @@ #include <lib/phy/adr.H> #include <lib/phy/seq.H> #include <lib/fir/check.H> +#include <lib/ccs/ccs_nimbus.H> #include <lib/workarounds/dp16_workarounds.H> #include <lib/workarounds/wr_vref_workarounds.H> #include <lib/dimm/ddr4/latch_wr_vref.H> @@ -1038,9 +1039,9 @@ fapi2::ReturnCode execute_cal_steps_helper( const fapi2::Target<TARGET_TYPE_MCA> const uint64_t i_total_cycles) { const auto& l_mcbist = mss::find_target<TARGET_TYPE_MCBIST>(i_target); - auto l_cal_inst = mss::ccs::initial_cal_command<TARGET_TYPE_MCBIST>(i_rp); + auto l_cal_inst = mss::ccs::initial_cal_command(i_rp); - mss::ccs::program<TARGET_TYPE_MCBIST, TARGET_TYPE_MCA> l_program; + ccs::program l_program; FAPI_DBG("%s executing training CCS instruction: 0x%016llx, 0x%016llx for cal config 0x%16x", mss::c_str(i_target), @@ -1337,7 +1338,7 @@ fapi_try_exit: template<> fapi2::ReturnCode setup_wr_level_terminations( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, const uint64_t i_rp, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { // Danger: Make sure this DIMM target doesn't get used/accessed until it is populated // by get_dimm_target_from_rank below! @@ -1396,7 +1397,7 @@ fapi_try_exit: template<> fapi2::ReturnCode restore_mainline_terminations( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, const uint64_t i_rp, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { // Danger: Make sure this DIMM target doesn't get used/accessed until it is populated // by get_dimm_target_from_rank below! |
