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| author | Jacob Harvey <jlharvey@us.ibm.com> | 2017-07-10 16:42:09 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-08-18 10:52:26 -0400 |
| commit | 25a46875b4bd8e7da5d5b2e342467ee2183e228b (patch) | |
| tree | 0a5f26174ebbcb86dbe1fb407b79404dfa9a7708 /src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C | |
| parent | d4c08be2b76339d60f098968bfe05f5a34a19c0b (diff) | |
| download | talos-hostboot-25a46875b4bd8e7da5d5b2e342467ee2183e228b.tar.gz talos-hostboot-25a46875b4bd8e7da5d5b2e342467ee2183e228b.zip | |
L3 work for mss xmls
mss_spd, mss_volt, mss_general, mss_data_buffer, mss_update_errors
Change-Id: I1252d6d11900e88e0842c234c5ed815063e68ec0
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42962
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44229
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C index 5755589ac..3d19b1764 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C @@ -261,7 +261,7 @@ fapi2::ReturnCode setup_phase_rotator_control_registers( const fapi2::Target<TAR // From the DDR PHY workbook constexpr uint64_t CONTINUOUS_UPDATE = 0x8024; - FAPI_INF("continuous update: 0x%x", CONTINUOUS_UPDATE); + FAPI_INF("%s continuous update: 0x%x", mss::c_str(i_target), CONTINUOUS_UPDATE); constexpr uint64_t SIM_OVERRIDE = 0x8080; constexpr uint64_t PHASE_CNTL_EN = 0x8020; @@ -302,7 +302,7 @@ fapi2::ReturnCode setup_phase_rotator_control_registers( const fapi2::Target<TAR // All the MCA (and both registers) will be in the same state, so we can get the first and use it to create the // values for the others. - FAPI_INF("Write 0x%lx into the ADR SysClk Phase Rotator Control Regs", l_update); + FAPI_INF("%s Write 0x%lx into the ADR SysClk Phase Rotator Control Regs", mss::c_str(i_target), l_update); // WRCLK Phase rotators are taken care of in the phy initfile. BRS 6/16. @@ -1482,7 +1482,7 @@ fapi2::ReturnCode setup_wr_level_terminations( const fapi2::Target<fapi2::TARGET FAPI_TRY( mss::rank::get_ranks_in_pair(i_target, i_rp, l_ranks) ); FAPI_ASSERT( !l_ranks.empty(), fapi2::MSS_NO_RANKS_IN_RANK_PAIR() - .set_TARGET(i_target) + .set_MCA_TARGET(i_target) .set_RANK_PAIR(i_rp), "No ranks configured in MCA %s, rank pair %d", mss::c_str(i_target), @@ -1541,7 +1541,7 @@ fapi2::ReturnCode restore_mainline_terminations( const fapi2::Target<fapi2::TARG FAPI_TRY( mss::rank::get_ranks_in_pair(i_target, i_rp, l_ranks) ); FAPI_ASSERT( !l_ranks.empty(), fapi2::MSS_NO_RANKS_IN_RANK_PAIR() - .set_TARGET(i_target) + .set_MCA_TARGET(i_target) .set_RANK_PAIR(i_rp), "No ranks configured in MCA %s, rank pair %d", mss::c_str(i_target), i_rp ); |
