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| author | Tsung Yeung <tyeung@us.ibm.com> | 2019-04-08 22:11:40 -0400 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2019-04-15 09:33:47 -0500 |
| commit | fa0064292733ea0c5091de493ea52845ba8d9ecd (patch) | |
| tree | a1ab4e8e2e4d3aaad21579e5706c47d2d2053406 /src/import/chips/p9/procedures/hwp/memory/lib/mc | |
| parent | 7c4068b510e172eb973b8e460ee432e7e8bc8275 (diff) | |
| download | talos-hostboot-fa0064292733ea0c5091de493ea52845ba8d9ecd.tar.gz talos-hostboot-fa0064292733ea0c5091de493ea52845ba8d9ecd.zip | |
Ignore refresh overrun fir NVDIMM during post-restore sequence
While CCS is running (ccs_addr_sel_mux=1) mainline refreshes could get
queued up and later released 1 cycle apart, causing the refresh overrun
fir. Mask this error during post-restore sequence so it doesn't get called
out later.
Change-Id: Iac0f998bfcc807d6f5fa2e6a57ec07a7afa5cc60
CQ:SW462190
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75692
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75696
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/mc')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H index 252ebc5a9..45ffbee13 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H @@ -85,6 +85,8 @@ class portTraits<mss::mc_type::NIMBUS> static constexpr uint64_t CAL3Q_REG = MCA_MBA_CAL3Q; static constexpr uint64_t DSM0Q_REG = MCA_MBA_DSM0Q; static constexpr uint64_t FWMS_REG = MCA_FWMS0; + static constexpr uint64_t CALFIRQ = MCA_MBACALFIRQ; + static constexpr uint64_t CALFIRMASK = MCA_MBACALFIR_MASK; // Danger Will Robinson <wave robot arms> MCA_DDRPHY_PC_PER_ZCAL_CONFIG_P0 uses PHY rank ordinal numbers // which are different between PHYs. So if you're playing with this register, be sure to map rank numbers. @@ -238,6 +240,9 @@ class portTraits<mss::mc_type::NIMBUS> CAL3Q_ALL_PERIODIC_LENGTH_LEN = MCA_MBA_CAL3Q_CFG_ALL_PERIODIC_LENGTH_LEN, CAL3Q_FREEZE_ON_PARITY_ERROR_DIS = MCA_MBA_CAL3Q_CFG_FREEZE_ON_PARITY_ERROR_DIS, + CALFIRQ_REFRESH_OVERRUN = MCA_MBACALFIRQ_REFRESH_OVERRUN, + CALFIRMASK_REFRESH_OVERRUN = MCA_MBACALFIR_MASK_REFRESH_OVERRUN, + RECR_ENABLE_UE_NOISE_WINDOW = MCA_RECR_MBSECCQ_ENABLE_UE_NOISE_WINDOW, RECR_TCE_CORRECTION = MCA_RECR_MBSECCQ_ENABLE_TCE_CORRECTION, RECR_READ_POINTER_DLY = MCA_RECR_MBSECCQ_READ_POINTER_DELAY, |
