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| author | Stephen Glancy <sglancy@us.ibm.com> | 2019-05-01 11:46:02 -0400 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2019-05-07 15:48:42 -0500 |
| commit | a38021c7fa7330016c23a50e492f7e42207904e2 (patch) | |
| tree | d8c5d1ef0dc4f0946d7972b490c576bb044bc1a6 /src/import/chips/p9/procedures/hwp/memory/lib/mc | |
| parent | 081679022f978b41f7764b50fe5b9e741b0d2ce3 (diff) | |
| download | talos-hostboot-a38021c7fa7330016c23a50e492f7e42207904e2.tar.gz talos-hostboot-a38021c7fa7330016c23a50e492f7e42207904e2.zip | |
Fixes RCD parity CID configuration
Change-Id: Ia0751e23bb1c1dbfd658c3f392ae11dd57669921
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76811
Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76875
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/mc')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H index 98cf5f7b2..d89bf89b0 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H @@ -685,7 +685,7 @@ fapi2::ReturnCode configure_cid_parity( const fapi2::Target<T>& i_target) l_state = mss::states::OFF_N; } - FAPI_DBG( "Change RDTAG_DLY to %d for %s", l_state, mss::c_str(i_target) ); + FAPI_DBG( "Change CID_PARITY to %d for %s", l_state, mss::c_str(i_target) ); FAPI_TRY( read_farb1q_register(i_target, l_data) ); set_cid_parity<T>(l_state, l_data); |
