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| author | Brian Silver <bsilver@us.ibm.com> | 2016-04-25 09:24:34 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-05-03 18:36:19 -0400 |
| commit | 1c3233db39fad9fe7e4799f65823bf115afb872d (patch) | |
| tree | 4ec58fb047822ee2af3a853e11afc818295848ad /src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C | |
| parent | 8ef2e43b09194df457a8cf44978117637a054238 (diff) | |
| download | talos-hostboot-1c3233db39fad9fe7e4799f65823bf115afb872d.tar.gz talos-hostboot-1c3233db39fad9fe7e4799f65823bf115afb872d.zip | |
Add 8Gb DRAM support
Change-Id: Ia2ba89169b1bdfe746bce29f5e6c32ef14b2e11c
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23720
Tested-by: Jenkins Server
Tested-by: Hostboot CI
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23722
Tested-by: FSP CI Jenkins
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C index 6d3ed7568..69b2bd568 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C @@ -94,8 +94,6 @@ fapi2::ReturnCode mc<TARGET_TYPE_MCS>::setup_xlate_map(const fapi2::Target<TARGE // Get the translation array, based on this specific DIMM's config dimm::kind l_dimm(d); - // TK: Get the information from the translation table for this DIMM. - FAPI_DBG("address translation for DIMM %s %dR %dgbx%d in slot %d", mss::c_str(d), l_dimm.iv_master_ranks, l_dimm.iv_dram_density, l_dimm.iv_dram_width, l_slot); @@ -142,20 +140,26 @@ fapi2::ReturnCode mc<TARGET_TYPE_MCS>::setup_xlate_map(const fapi2::Target<TARGE } - // Tell the MC which of the row bits are valid. + // Tell the MC which of the row bits are valid, and map the DIMM selector if (l_dimm.iv_rows >= 16) { l_xlate.setBit(MCS_PORT02_MCP0XLT0_SLOT0_ROW15_VALID + l_slot_offset); + l_xlate.insertFromRight<MCS_PORT02_MCP0XLT0_R15_BIT_MAP, MCS_PORT02_MCP0XLT0_R15_BIT_MAP_LEN>(0b00110); + l_xlate.insertFromRight<MCS_PORT02_MCP0XLT0_D_BIT_MAP, MCS_PORT02_MCP0XLT0_D_BIT_MAP_LEN>(0b00101); } if (l_dimm.iv_rows >= 17) { l_xlate.setBit(MCS_PORT02_MCP0XLT0_SLOT0_ROW16_VALID + l_slot_offset); + l_xlate.insertFromRight<MCS_PORT02_MCP0XLT0_R16_BIT_MAP, MCS_PORT02_MCP0XLT0_R16_BIT_MAP_LEN>(0b00101); + l_xlate.insertFromRight<MCS_PORT02_MCP0XLT0_D_BIT_MAP, MCS_PORT02_MCP0XLT0_D_BIT_MAP_LEN>(0b00100); } if (l_dimm.iv_rows >= 18) { l_xlate.setBit(MCS_PORT02_MCP0XLT0_SLOT0_ROW17_VALID + l_slot_offset); + l_xlate.insertFromRight<MCS_PORT02_MCP0XLT0_R17_BIT_MAP, MCS_PORT02_MCP0XLT0_R17_BIT_MAP_LEN>(0b00100); + l_xlate.insertFromRight<MCS_PORT02_MCP0XLT0_D_BIT_MAP, MCS_PORT02_MCP0XLT0_D_BIT_MAP_LEN>(0b00011); } } @@ -172,8 +176,7 @@ fapi2::ReturnCode mc<TARGET_TYPE_MCS>::setup_xlate_map(const fapi2::Target<TARGE // Master rank 0, 1 bit maps are ignored. // Row 16,17 bit maps are ignored. // Row 15 maps to Port Address bit 6 - l_xlate.insertFromRight<MCS_PORT02_MCP0XLT0_D_BIT_MAP, MCS_PORT02_MCP0XLT0_D_BIT_MAP_LEN>(0b00101); - l_xlate.insertFromRight<MCS_PORT02_MCP0XLT0_R15_BIT_MAP, MCS_PORT02_MCP0XLT0_R15_BIT_MAP_LEN>(0b00110); + // Drop down the column assignments l_xlate1.insertFromRight<MCS_PORT02_MCP0XLT1_COL4_BIT_MAP, |
