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author | Andre Marin <aamarin@us.ibm.com> | 2016-04-19 20:15:17 -0500 |
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committer | William G. Hoffa <wghoffa@us.ibm.com> | 2016-05-11 09:10:14 -0400 |
commit | 1bd59b5cc9349785ceae0a8dd2666aa26f6a29e9 (patch) | |
tree | dad19cc933d5d7e41bba16914de51ecbe9a3988e /src/import/chips/p9/procedures/hwp/memory/lib/freq | |
parent | 849f46048d5b4cd1b969d129b3f04e36bf3ddbc5 (diff) | |
download | talos-hostboot-1bd59b5cc9349785ceae0a8dd2666aa26f6a29e9.tar.gz talos-hostboot-1bd59b5cc9349785ceae0a8dd2666aa26f6a29e9.zip |
Fix throttle procedure & MSS attribute clean up
Change-Id: I04e1a3d5303a1ce56b4951b22442f2d28c89298c
Original-Change-Id: I7b545b65aaf9cdfea08ab2c5142898f5c971a74b
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23486
Tested-by: Jenkins Server
Tested-by: Hostboot CI
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24327
Tested-by: FSP CI Jenkins
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/freq')
-rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/freq/cas_latency.C | 33 | ||||
-rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/freq/cas_latency.H | 10 |
2 files changed, 23 insertions, 20 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/freq/cas_latency.C b/src/import/chips/p9/procedures/hwp/memory/lib/freq/cas_latency.C index 04551ae4f..5d5a0c8b8 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/freq/cas_latency.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/freq/cas_latency.C @@ -149,12 +149,14 @@ fapi2::ReturnCode cas_latency::find_CL(const fapi2::Target<fapi2::TARGET_TYPE_MC //Chose an actual CAS Latency (CLactual) that is greater than or equal to CLdesired //and is supported by all modules on the memory channel - FAPI_TRY( choose_actual_CL(l_supported_CLs, iv_largest_taamin, iv_proposed_tck, l_desired_cas_latency) ); + FAPI_TRY( choose_actual_CL(l_supported_CLs, iv_largest_taamin, iv_proposed_tck, l_desired_cas_latency), + "Failed choose_actual_CL()"); // Once the calculation of CLactual is completed, the BIOS must also // verify that this CAS Latency value does not exceed tAAmax. //If not, choose a lower CL value and repeat until a solution is found. - FAPI_TRY( validate_valid_CL(l_supported_CLs, iv_largest_taamin, iv_proposed_tck, l_desired_cas_latency) ); + FAPI_TRY( validate_valid_CL(l_supported_CLs, iv_largest_taamin, iv_proposed_tck, l_desired_cas_latency), + "Failed validate_valid_CL()"); // Update output values after all criteria is met o_cas_latency = l_desired_cas_latency; @@ -420,21 +422,16 @@ inline bool cas_latency::is_CL_exceeding_tAAmax(const uint64_t i_cas_latency, /// -/// @brief Helper function to determines next lowest CAS latency (CL) -/// @param[in] i_common_CLs vector of common CAS latencies -/// @param[in,out] io_desired_cas_latency current CAS latency -/// @return the next lowest CL +/// @brief Helper function to determines next lowest CAS latency (CL) +/// @param[in] i_common_CLs vector of common CAS latencies +/// @param[in] i_desired_cas_latency current CAS latency +/// @return the next lowest CL /// inline uint64_t cas_latency::next_lowest_CL(const std::vector<uint64_t>& i_common_CLs, - uint64_t& io_desired_cas_latency) + const uint64_t i_desired_cas_latency) { - auto iterator = std::lower_bound(i_common_CLs.begin(), - i_common_CLs.end(), - io_desired_cas_latency); - - io_desired_cas_latency = *(--iterator); - - return io_desired_cas_latency; + auto iterator = std::lower_bound(i_common_CLs.begin(), i_common_CLs.end(), i_desired_cas_latency); + return *(--iterator); } /// @@ -453,6 +450,7 @@ fapi2::ReturnCode cas_latency::choose_actual_CL (const std::vector<uint64_t>& i_ { if( i_common_CLs.empty() ) { + FAPI_ERR("Common CAS latency vector is empty!"); return fapi2::FAPI2_RC_INVALID_PARAMETER; } @@ -472,6 +470,9 @@ fapi2::ReturnCode cas_latency::choose_actual_CL (const std::vector<uint64_t>& i_ l_is_CL_supported = is_CL_supported_in_common(i_common_CLs, io_desired_cas_lat); } + // If we reach here everything is okay + return fapi2::FAPI2_RC_SUCCESS; + fapi_try_exit: return fapi2::current_err; } @@ -492,6 +493,7 @@ fapi2::ReturnCode cas_latency::validate_valid_CL (const std::vector<uint64_t>& i { if( i_common_CLs.empty() ) { + FAPI_ERR("Common CAS latency vector is empty!"); return fapi2::FAPI2_RC_INVALID_PARAMETER; } @@ -504,10 +506,11 @@ fapi2::ReturnCode cas_latency::validate_valid_CL (const std::vector<uint64_t>& i // Decrement CL to next lowest supported CL // And try again io_desired_cas_lat = next_lowest_CL(i_common_CLs, io_desired_cas_lat); - FAPI_DBG("Next lowest supported CL: %d", io_desired_cas_lat); + FAPI_DBG("Next lowest CAS latency %d", io_desired_cas_lat); FAPI_TRY( choose_actual_CL(i_common_CLs, i_tAA, io_tCK, io_desired_cas_lat), "Failed choose_actual_CL()"); + l_is_CL_violating_spec = is_CL_exceeding_tAAmax (io_desired_cas_lat, io_tCK); } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/freq/cas_latency.H b/src/import/chips/p9/procedures/hwp/memory/lib/freq/cas_latency.H index b1772186b..381a6951e 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/freq/cas_latency.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/freq/cas_latency.H @@ -181,13 +181,13 @@ class cas_latency const uint64_t i_tCK) const; /// - /// @brief Helper function to determines next lowest CAS latency (CL) - /// @param[in] i_common_CLs vector of common CAS latencies - /// @param[in,out] io_desired_cas_latency current CAS latency - /// @return the next lowest CL + /// @brief Helper function to determines next lowest CAS latency (CL) + /// @param[in] i_common_CLs vector of common CAS latencies + /// @param[in] i_desired_cas_latency current CAS latency + /// @return the next lowest CL /// inline uint64_t next_lowest_CL(const std::vector<uint64_t>& i_common_CLs, - uint64_t& io_desired_cas_latency); + const uint64_t i_desired_cas_latency); /// /// @brief Checks that CAS latency (CL) is supported among all dimms |