diff options
| author | Brian Silver <bsilver@us.ibm.com> | 2016-10-13 09:51:57 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-10-16 21:40:15 -0400 |
| commit | 7326ad3c9b77f2adc19e58280b50934b69c16032 (patch) | |
| tree | d439631fa4784f6c7f2ca0f3e493077032f9c32e /src/import/chips/p9/procedures/hwp/memory/lib/eff_config | |
| parent | 7672512af9ddd64b5899ec41ba817905dd781730 (diff) | |
| download | talos-hostboot-7326ad3c9b77f2adc19e58280b50934b69c16032.tar.gz talos-hostboot-7326ad3c9b77f2adc19e58280b50934b69c16032.zip | |
Changes to limit DLL cal on spare DP8, stop CSS before starting
Enable parity after command for CCS
Disable parity via RC14
Enable DLL (MRS) enable
Send 0 value RCD
Repair clock-enable RCD control word
Change-Id: Id46a675afbc535989f7e0e451a084dfdc4d4a962
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31142
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Dev-Ready: Brian R. Silver <bsilver@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31170
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/eff_config')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C index ea214b833..92a5da74d 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C @@ -1299,6 +1299,8 @@ fapi_try_exit: /// fapi2::ReturnCode eff_config::dimm_rc14(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) { + constexpr uint8_t DISABLE_PARITY_MASK = 0b11111110; + // Targets const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target); const auto l_mca = find_target<TARGET_TYPE_MCA>(i_target); @@ -1307,14 +1309,19 @@ fapi2::ReturnCode eff_config::dimm_rc14(const fapi2::Target<TARGET_TYPE_DIMM>& i const auto l_port_num = index(l_mca); const auto l_dimm_num = index(i_target); + uint8_t l_hacked_rc14; + // Retrieve MCS attribute data uint8_t l_attrs_dimm_rc14[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {}; FAPI_TRY( eff_dimm_ddr4_rc14(l_mcs, &l_attrs_dimm_rc14[0][0]) ); + // Disable parity checking + l_hacked_rc14 = iv_pDecoder->iv_raw_card.iv_rc0e & DISABLE_PARITY_MASK; + // Update MCS attribute - l_attrs_dimm_rc14[l_port_num][l_dimm_num] = iv_pDecoder->iv_raw_card.iv_rc0e; + l_attrs_dimm_rc14[l_port_num][l_dimm_num] = l_hacked_rc14; - FAPI_INF( "%s: RC14 setting: %d", c_str(i_target), l_attrs_dimm_rc14[l_port_num][l_dimm_num] ); + FAPI_INF( "%s: RC14 setting: 0x%0x", c_str(i_target), l_attrs_dimm_rc14[l_port_num][l_dimm_num] ); FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_DDR4_RC14, l_mcs, l_attrs_dimm_rc14) ); fapi_try_exit: @@ -2000,8 +2007,8 @@ fapi2::ReturnCode eff_config::dll_reset(const fapi2::Target<TARGET_TYPE_DIMM>& i FAPI_TRY( eff_dram_dll_reset(l_mcs, &l_attrs_dll_reset[0][0]) ); - // Default is to not reset DLLs during IPL. - l_attrs_dll_reset[l_port_num][l_dimm_num] = fapi2::ENUM_ATTR_EFF_DRAM_DLL_RESET_NO; + // Default is to reset DLLs during IPL. + l_attrs_dll_reset[l_port_num][l_dimm_num] = fapi2::ENUM_ATTR_EFF_DRAM_DLL_RESET_YES; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_DLL_RESET, l_mcs, l_attrs_dll_reset), "Failed setting attribute for BL"); |
