Updates CCS to run with quad encoded chip select

Change-Id: I29566f1a77d244fa7cbd600e7a83da9784a66f51
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72720
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72928
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>

3 files changed, 9 insertions, 9 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H
index 0d7b2d018..bd8277daa 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H
@@ -308,7 +308,7 @@ fapi2::ReturnCode mrs_engine( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_ta
                               const uint64_t i_delay_in_cycles,
                               std::vector< ccs::instruction_t<T> >& io_inst )
 {
-    ccs::instruction_t<T> l_inst_a_side = ccs::mrs_command<T>(i_target, i_rank, i_data.iv_mrs);
+    ccs::instruction_t<T> l_inst_a_side = ccs::mrs_command<T>(i_rank, i_data.iv_mrs);
     ccs::instruction_t<T> l_inst_b_side;
     bool l_is_a17 = false;
 
@@ -1914,7 +1914,7 @@ fapi2::ReturnCode mpr_read( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_targ
     // Right now we only have support for RD and RDA
     // Unclear if we want the API select the type of read command right now
     // Note the auto precharge is ignored with MPR mode on so we just do a read cmd
-    ccs::instruction_t<T> l_inst = ccs::rd_command<T> (i_target, i_rank, i_mpr_loc);
+    ccs::instruction_t<T> l_inst = ccs::rd_command<T> (i_rank, i_mpr_loc);
 
     // In MPR Mode:
     // Reads (back-to-back) from Page 0 may use tCCD_S or tCCD_L timing between read commands
@@ -1959,7 +1959,7 @@ fapi2::ReturnCode precharge_all( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i
                                  const uint64_t i_rank,
                                  std::vector< ccs::instruction_t<T> >& io_inst )
 {
-    ccs::instruction_t<T> l_inst = ccs::precharge_all_command<T> (i_target, i_rank);
+    ccs::instruction_t<T> l_inst = ccs::precharge_all_command<T> (i_rank);
 
     // From the DDR4 Spec tRP is the precharge command period
     uint8_t l_delay = 0;
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C
index 0374da3dc..b35c5084f 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C
@@ -527,9 +527,9 @@ fapi2::ReturnCode post_restore_zqcal( const fapi2::Target<fapi2::TARGET_TYPE_MCA
         for ( const auto r : l_ranks)
         {
             FAPI_DBG("precharge_all_command for %s", mss::c_str(d));
-            l_program.iv_instructions.push_back( ccs::precharge_all_command<TARGET_TYPE_MCBIST>(d, r, l_trp[0]) );
+            l_program.iv_instructions.push_back( ccs::precharge_all_command<TARGET_TYPE_MCBIST>(r, l_trp[0]) );
             FAPI_DBG("zqcal_command for %s", mss::c_str(d));
-            l_program.iv_instructions.push_back( ccs::zqcl_command<TARGET_TYPE_MCBIST>(d, r, mss::tzqinit()) );
+            l_program.iv_instructions.push_back( ccs::zqcl_command<TARGET_TYPE_MCBIST>(r, mss::tzqinit()) );
         }
     }// dimms
 
@@ -661,7 +661,7 @@ fapi2::ReturnCode preload_epow_sequence( const fapi2::Target<fapi2::TARGET_TYPE_
 
     // Precharge all command
     // All CKE = high, all CSn = low, Reset_n = high, wait tRP
-    l_inst = ccs::precharge_all_command<TARGET_TYPE_MCBIST>(l_dimms[0], 0, l_trp);
+    l_inst = ccs::precharge_all_command<TARGET_TYPE_MCBIST>(0, l_trp);
     l_inst.arr0.insertFromRight<TT::ARR0_DDR_CSN_0_1, TT::ARR0_DDR_CSN_0_1_LEN>(CS_N_ACTIVE);
     l_inst.arr0.insertFromRight<TT::ARR0_DDR_CSN_2_3, TT::ARR0_DDR_CSN_2_3_LEN>(CS_N_ACTIVE);
     l_inst.arr0.setBit<TT::ARR0_DDR_RESETN>();
@@ -670,7 +670,7 @@ fapi2::ReturnCode preload_epow_sequence( const fapi2::Target<fapi2::TARGET_TYPE_
 
     // Self-refresh entry command
     // All CKE = low, all CSn = low, Reset_n = high, wait tCKSRE
-    l_inst = ccs::self_refresh_entry_command<TARGET_TYPE_MCBIST>(l_dimms[0], 0, mss::tcksre(l_dimms[0]));
+    l_inst = ccs::self_refresh_entry_command<TARGET_TYPE_MCBIST>(0, mss::tcksre(l_dimms[0]));
     l_inst.arr0.insertFromRight<TT::ARR0_DDR_CSN_0_1, TT::ARR0_DDR_CSN_0_1_LEN>(CS_N_ACTIVE);
     l_inst.arr0.insertFromRight<TT::ARR0_DDR_CSN_2_3, TT::ARR0_DDR_CSN_2_3_LEN>(CS_N_ACTIVE);
     l_inst.arr0.insertFromRight<TT::ARR0_DDR_CKE, TT::ARR0_DDR_CKE_LEN>(mss::CKE_LOW);
@@ -680,7 +680,7 @@ fapi2::ReturnCode preload_epow_sequence( const fapi2::Target<fapi2::TARGET_TYPE_
 
     // Push in an empty instruction for RESETn
     // All CKE = low, all CSn = high (default), Reset_n = low
-    l_inst = ccs::instruction_t<TARGET_TYPE_MCBIST>(l_dimms[0]);
+    l_inst = ccs::instruction_t<TARGET_TYPE_MCBIST>();
     FAPI_INF("Assert RESETn arr0 = 0x%016lx , arr1 = 0x%016lx", l_inst.arr0, l_inst.arr1);
     l_program.iv_instructions.push_back(l_inst);
 
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.C
index 844765f44..6e53bddd8 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.C
@@ -69,7 +69,7 @@ fapi2::ReturnCode setup_dram_zqcal( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>
     FAPI_TRY( mss::tdllk(i_target, tDLLK) );
 
     // Note: this isn't general - assumes Nimbus via MCBIST instruction here BRS
-    l_inst = ccs::zqcl_command<TARGET_TYPE_MCBIST>(i_target, i_rank);
+    l_inst = ccs::zqcl_command<TARGET_TYPE_MCBIST>(i_rank);
 
     // Doubling tZQ to better margin per lab request
     {