Adds LRDIMM DWL training step

Change-Id: I0fe9a777722cec85249a558a37a90b1eaaf7cd0a
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67525
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68560
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

2 files changed, 70 insertions, 1 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H
index 3c5671bf4..49d0b68e7 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H
@@ -1518,6 +1518,40 @@ fapi2::ReturnCode mrs_load( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_targ
                             std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst);
 
 ///
+/// @brief Sets WR LVL mode
+/// @param[in] i_target a DIMM target
+/// @param[in] i_mode setting for WR LVL mode
+/// @param[in,out] io_data data we are modifying MPR mode to
+/// @return FAPI2_RC_SUCCESS if and only if ok
+///
+inline fapi2::ReturnCode set_wr_lvl_mode(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+        const mss::states i_mode,
+        mrs01_data& io_data)
+{
+    constexpr uint64_t MAX_WR_LVL_MODE = 0b1;
+
+    FAPI_ASSERT( i_mode <= MAX_WR_LVL_MODE,
+                 fapi2::MSS_BAD_MR_PARAMETER()
+                 .set_MR_NUMBER(MRS_LOAD)
+                 .set_PARAMETER(WR_LVL)
+                 .set_PARAMETER_VALUE(i_mode)
+                 .set_DIMM_IN_ERROR(i_target),
+                 "%s Invalid WR LVL Mode recieved: %d. Max encoding allowed: %d.",
+                 mss::c_str(i_target),
+                 i_mode,
+                 MAX_WR_LVL_MODE);
+
+    // Update field if input check passes
+    io_data.iv_wl_enable = i_mode == mss::states::ON ?
+                           fapi2::ENUM_ATTR_EFF_DRAM_WR_LVL_ENABLE_ENABLE :
+                           fapi2::ENUM_ATTR_EFF_DRAM_WR_LVL_ENABLE_DISABLE;
+
+    return fapi2::FAPI2_RC_SUCCESS;
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
 /// @brief Set MPR Mode
 /// @param[in] i_target a DIMM target
 /// @param[in] i_mode setting for MPR mode
@@ -1684,6 +1718,40 @@ fapi_try_exit:
 }
 
 ///
+/// @brief Makes CCS instruction to set WR LVL Mode
+/// @tparam T TargetType of the CCS instruction
+/// @param[in] i_target a DIMM target
+/// @param[in] i_mode setting for WR LVL mode
+/// @param[in] i_rank DIMM rank
+/// @param[in,out] io_inst a vector of CCS instructions we should add to
+/// @return FAPI2_RC_SUCCESS if and only if ok
+///
+template< fapi2::TargetType T >
+fapi2::ReturnCode wr_lvl(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+                         const mss::states i_mode,
+                         const uint64_t i_rank,
+                         std::vector< ccs::instruction_t<T> >& io_inst )
+{
+    // Spec states we need to use tmod for our delay, so we do
+    const uint64_t l_delay = mss::tmod(i_target);
+
+    mrs01_data l_data(i_target, fapi2::current_err);
+    FAPI_TRY(fapi2::current_err, "%s. Failed to initialize mrs01_data for set_wr_lvl_mode", mss::c_str(i_target) );
+
+    FAPI_TRY( set_wr_lvl_mode(i_target, i_mode, l_data),
+              "%s. Failed set_wr_lvl_mode() with a setting of %d",
+              mss::c_str(i_target), i_mode);
+
+    // Make MRS CCS inst
+    FAPI_TRY( mrs_engine(i_target, l_data, i_rank, l_delay, io_inst),
+              "Failed to send MRS01 on %s, rank: %d, delay (in cycles): %d",
+              mss::c_str(i_target), i_rank, l_delay);
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
 /// @brief Makes CCS instruction to set MPR Mode
 /// @tparam T TargetType of the CCS instruction
 /// @param[in] i_target a DIMM target
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.H
index bcfdb2803..2b0418cfb 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2018                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -69,6 +69,7 @@ enum mrs_bad_field
     RTT_WR = 12,
     MPR_PAGE = 13,
     MPR_MODE = 14,
+    WR_LVL = 15,
 
     // Following is for MR_NUMBER entry into the BAD_MR_PARAM ffdc
     // Set to random value so it won't be confused with an actual MR number