Enable median rank wr_vref value on NVDIMM

- The NVDIMM restore procedure is required to restore the wr vref values.
The current method is to latch in the per-dram wr vref value with PDA.
However, this requires multiple CCS sequences due to hardware limitation
and would break refresh timing between sequences, introduce possible UEs.
To get around this, we will use the median value of all the drams per
rank-pair instead of per-dram value.

Previous attempt was to use average value but after the speaking with
Stephen G. median value is a better approach due to the possibility
that bad vref value from failing dram

- Added NVDIMM-specifc CCS execute procedure

Change-Id: Ie7d1e063c423a4374ca22422395ee5524d70a124
CQ:SW459457
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/74753
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/74790
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

6 files changed, 132 insertions, 97 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.C
index def06a0df..0d2cad989 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2019                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -39,6 +39,7 @@
 #include <lib/dimm/ddr4/mrs_load_ddr4.H>
 #include <lib/dimm/ddr4/latch_wr_vref.H>
 #include <lib/dimm/rank.H>
+#include <lib/workarounds/ccs_workarounds.H>
 
 using fapi2::TARGET_TYPE_MCBIST;
 using fapi2::TARGET_TYPE_DIMM;
@@ -96,13 +97,14 @@ fapi_try_exit:
 /// @param[in] i_rank_pair, rank pair on which to latch MRS 06 - hits all ranks in the rank pair
 /// @param[in] i_train_range, VREF range to setup
 /// @param[in] i_train_value, VREF value to setup
-/// @param[in,out] a vector of CCS instructions we should add to
+/// @param[in] i_nvdimm_workaround switch to indicate nvdimm workaround. Default to false
 /// @return FAPI2_RC_SUCCESS if and only if ok
 ///
 fapi2::ReturnCode latch_wr_vref_commands_by_rank_pair( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         const uint64_t i_rank_pair,
         const uint8_t i_train_range,
-        const uint8_t i_train_value)
+        const uint8_t i_train_value,
+        const bool i_nvdimm_workaround)
 {
     // Declares variables
     const auto l_mcbist = find_target<fapi2::TARGET_TYPE_MCBIST>(i_target);
@@ -141,7 +143,17 @@ fapi2::ReturnCode latch_wr_vref_commands_by_rank_pair( const fapi2::Target<fapi2
     }
 
     // Executes the CCS commands
-    FAPI_TRY( mss::ccs::execute(l_mcbist, l_program, i_target), "Failed ccs execute %s", mss::c_str(i_target) );
+    // Run the NVDIMM-specific execute procedure if this is for nvdimm workaround.
+    // Otherwise, execute as usual.
+    if (i_nvdimm_workaround)
+    {
+        FAPI_TRY( mss::ccs::workarounds::nvdimm::execute(l_mcbist, l_program, i_target), "Failed ccs execute %s",
+                  mss::c_str(i_target) );
+    }
+    else
+    {
+        FAPI_TRY( mss::ccs::execute(l_mcbist, l_program, i_target), "Failed ccs execute %s", mss::c_str(i_target) );
+    }
 
 fapi_try_exit:
     return fapi2::current_err;
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.H
index 39536d566..0cb2a285e 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2019                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -73,13 +73,14 @@ fapi2::ReturnCode add_latch_wr_vref_commands( const fapi2::Target<fapi2::TARGET_
 /// @param[in] i_rank_pair, rank pair on which to latch MRS 06 - hits all ranks in the rank pair
 /// @param[in] i_train_range, VREF range to setup
 /// @param[in] i_train_value, VREF value to setup
-/// @param[in,out] a vector of CCS instructions we should add to
+/// @param[in] i_nvdimm_workaround switch to indicate nvdimm workaround. Default to false
 /// @return FAPI2_RC_SUCCESS if and only if ok
 ///
 fapi2::ReturnCode latch_wr_vref_commands_by_rank_pair( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         const uint64_t i_rank_pair,
         const uint8_t i_train_range,
-        const uint8_t i_train_value);
+        const uint8_t i_train_value,
+        const bool i_nvdimm_workaround = false);
 
 ///
 /// @brief enables VREF train enable in an MRS06 class
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C
index ed63071d5..fe2f396f1 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C
@@ -53,8 +53,8 @@
 #include <lib/mc/port.H>
 #include <lib/phy/dp16.H>
 #include <lib/dimm/mrs_load.H>
-#include <lib/dimm/ddr4/pda.H>
 #include <lib/dimm/ddr4/zqcal.H>
+#include <lib/dimm/ddr4/latch_wr_vref.H>
 #include <lib/dimm/ddr4/control_word_ddr4.H>
 #include <lib/workarounds/ccs_workarounds.H>
 #include <lib/eff_config/timing.H>
@@ -322,70 +322,6 @@ fapi_try_exit:
 }
 
 ///
-/// @brief PDA support for post restore transition
-/// Specialization for TARGET_TYPE_DIMM
-/// @param[in] i_target the target associated with this subroutine
-/// @return FAPI2_RC_SUCCESS iff setup was successful
-///
-template<>
-fapi2::ReturnCode pda_vref_latch( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target )
-{
-    std::vector<uint64_t> l_ranks;
-    const auto& l_mca = mss::find_target<TARGET_TYPE_MCA>(i_target);
-    fapi2::buffer<uint8_t> l_value, l_range;
-    fapi2::ReturnCode l_rc(fapi2::FAPI2_RC_SUCCESS);
-
-    // Creates the MRS container class
-    mss::ddr4::pda::commands<mss::ddr4::mrs06_data> l_container;
-
-    // Get all the ranks in the dimm
-    mss::rank::ranks(i_target, l_ranks);
-
-    // Get the number of DRAMs
-    uint8_t l_width = 0;
-    mss::eff_dram_width(i_target, l_width);
-    const uint64_t l_num_drams = (l_width == fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8) ? MAX_DRAMS_X8 : MAX_DRAMS_X4;
-
-    for (const auto& l_rank : l_ranks)
-    {
-
-        uint64_t l_rp = 0;
-        uint64_t l_wr_vref_value = 0;
-        bool l_wr_vref_range = 0;
-        fapi2::buffer<uint64_t> l_data ;
-
-        mss::rank::get_pair_from_rank(l_mca, l_rank, l_rp);
-
-        // create mrs06
-        mss::ddr4::mrs06_data l_mrs(i_target, l_rc);
-
-        // loop through all the dram
-        for(uint64_t l_dram = 0; l_dram < l_num_drams; l_dram++)
-        {
-            mss::dp16::wr_vref::read_wr_vref_register( l_mca, l_rp, l_dram, l_data);
-            mss::dp16::wr_vref::get_wr_vref_range( l_data, l_dram, l_wr_vref_range);
-            mss::dp16::wr_vref::get_wr_vref_value( l_data, l_dram, l_wr_vref_value);
-
-            l_mrs.iv_vrefdq_train_value[mss::index(l_rank)] = l_wr_vref_value;
-            l_mrs.iv_vrefdq_train_range[mss::index(l_rank)] = l_wr_vref_range;
-            l_container.add_command(i_target, l_rank, l_mrs, l_dram);
-        }
-    }
-
-    // Disable refresh
-    FAPI_TRY( mss::change_refresh_enable(l_mca, states::LOW) );
-
-    // execute_wr_vref_latch(l_container)
-    FAPI_TRY( mss::ddr4::pda::execute_wr_vref_latch(l_container) )
-
-    // Enable refresh
-    FAPI_TRY( mss::change_refresh_enable(l_mca, states::HIGH) );
-
-fapi_try_exit:
-    return fapi2::current_err;
-}
-
-///
 /// @brief Disable powerdown mode in rc09
 /// @param[in] i_target, a fapi2::Target<TARGET_TYPE_DIMM>
 /// @param[in,out] io_inst a vector of CCS instructions we should add to
@@ -540,7 +476,7 @@ fapi2::ReturnCode rcd_restore( const fapi2::Target<TARGET_TYPE_MCA>& i_target )
     // Exit STR first so CKE is back to high and rcd isn't ignoring us
     FAPI_TRY( self_refresh_exit( i_target ) );
 
-    FAPI_TRY( ccs::execute(l_mcbist, l_program, i_target),
+    FAPI_TRY( mss::ccs::workarounds::nvdimm::execute(l_mcbist, l_program, i_target),
               "Failed to execute ccs for %s", mss::c_str(i_target) );
 
     // Now, drive CKE back to low via STR entry instead of pde (we have data in the drams!)
@@ -557,7 +493,7 @@ fapi2::ReturnCode rcd_restore( const fapi2::Target<TARGET_TYPE_MCA>& i_target )
     }// dimms
 
     // Restore the rcd
-    FAPI_TRY( ccs::execute(l_mcbist, l_program, i_target),
+    FAPI_TRY( mss::ccs::workarounds::nvdimm::execute(l_mcbist, l_program, i_target),
               "Failed to execute ccs for %s", mss::c_str(i_target) );
 
 fapi_try_exit:
@@ -597,7 +533,7 @@ fapi2::ReturnCode post_restore_zqcal( const fapi2::Target<fapi2::TARGET_TYPE_MCA
     }// dimms
 
     // execute ZQCAL instructions
-    FAPI_TRY( mss::ccs::execute(l_mcbist, l_program, i_target),
+    FAPI_TRY( mss::ccs::workarounds::nvdimm::execute(l_mcbist, l_program, i_target),
               "Failed to execute ccs for ZQCAL %s", mss::c_str(i_target) );
 
 fapi_try_exit:
@@ -605,6 +541,46 @@ fapi_try_exit:
 }
 
 ///
+/// @brief Latch write vref
+/// @param[in] i_target the target associated with this subroutine
+/// @return FAPI2_RC_SUCCESS iff setup was successful
+///
+fapi2::ReturnCode wr_vref_latch( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target )
+{
+    std::vector<uint64_t> l_pairs;
+    const bool NVDIMM_WORKAROUND = true;
+
+    // We are latching in the averaged value and we should have the averaged value
+    // (this step should be run after all the draminit) so just the first dram is fine
+    constexpr uint64_t l_dram = 0;
+
+    // Get our rank pairs.
+    FAPI_TRY( mss::rank::get_rank_pairs(i_target, l_pairs) );
+
+    for (const auto& l_rp : l_pairs)
+    {
+        FAPI_INF("NVDIMM wr_vref_latch on rp %d %s", l_rp, mss::c_str(i_target));
+        fapi2::buffer<uint64_t> l_data ;
+        uint64_t l_wr_vref_value = 0;
+        bool l_wr_vref_range = 0;
+
+        mss::dp16::wr_vref::read_wr_vref_register( i_target, l_rp, l_dram, l_data);
+        mss::dp16::wr_vref::get_wr_vref_range( l_data, l_dram, l_wr_vref_range);
+        mss::dp16::wr_vref::get_wr_vref_value( l_data, l_dram, l_wr_vref_value);
+
+        FAPI_TRY( mss::ddr4::latch_wr_vref_commands_by_rank_pair(i_target,
+                  l_rp,
+                  l_wr_vref_range,
+                  l_wr_vref_value,
+                  NVDIMM_WORKAROUND) );
+
+    }// rank pairs
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
 /// @brief Post restore transition to support restoring nvdimm to
 /// a functional state after the restoring the data from NAND flash
 /// to DRAM
@@ -616,6 +592,7 @@ template<>
 fapi2::ReturnCode post_restore_transition( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target )
 {
     mss::states l_maint_addr_enabled = mss::states::LOW;
+    const bool NVDIMM_WORKAROUND = true;
 
     FAPI_TRY(get_maint_addr_mode_en(i_target, l_maint_addr_enabled));
 
@@ -633,16 +610,13 @@ fapi2::ReturnCode post_restore_transition( const fapi2::Target<fapi2::TARGET_TYP
     FAPI_TRY( self_refresh_exit( i_target ) );
 
     // Load the MRS
-    FAPI_TRY( mss::mrs_load( i_target ) );
+    FAPI_TRY( mss::mrs_load( i_target, NVDIMM_WORKAROUND ) );
 
     // Do ZQCAL
     FAPI_TRY( post_restore_zqcal(i_target) );
 
-    // Latch the trained PDA vref values for each dimm under the port
-    for (const auto& l_dimm : mss::find_targets<fapi2::TARGET_TYPE_DIMM>(i_target))
-    {
-        FAPI_TRY( pda_vref_latch( l_dimm ) );
-    }
+    // Latch in the rank averaged vref value
+    FAPI_TRY(wr_vref_latch(i_target));
 
     //Restore main_addr_mode_en to previous setting
     FAPI_TRY(change_maint_addr_mode_en(i_target, l_maint_addr_enabled));
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.H
index 538a650ba..5df44c13c 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.H
@@ -37,6 +37,7 @@
 #include <generic/memory/lib/utils/find.H>
 #include <lib/shared/mss_const.H>
 #include <lib/ccs/ccs.H>
+#include <lib/phy/dp16.H>
 
 namespace mss
 {
@@ -114,16 +115,6 @@ template< fapi2::TargetType T >
 fapi2::ReturnCode self_refresh_exit( const fapi2::Target<T>& i_target );
 
 ///
-/// @brief Latch write vref at per-dram basis
-/// @tparam T the target type associated with this subroutine
-/// @param[in] i_target the target associated with this subroutine
-/// @return FAPI2_RC_SUCCESS iff setup was successful
-///
-
-template< fapi2::TargetType T >
-fapi2::ReturnCode pda_vref_latch( const fapi2::Target<T>& i_target );
-
-///
 /// @brief Disable powerdown mode in rc09
 /// @param[in] i_target, a fapi2::Target<TARGET_TYPE_DIMM>
 /// @param[in,out] io_inst a vector of CCS instructions we should add to
@@ -163,6 +154,13 @@ fapi2::ReturnCode rcd_restore( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_ta
 fapi2::ReturnCode post_restore_zqcal( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target);
 
 ///
+/// @brief Latch write vref
+/// @param[in] i_target the target associated with this subroutine
+/// @return FAPI2_RC_SUCCESS iff setup was successful
+///
+fapi2::ReturnCode wr_vref_latch( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target );
+
+///
 /// @brief Full post-restore transition for NVDIMM
 /// @tparam T the target type associated with this subroutine
 /// @param[in] i_target the target associated with this subroutine
@@ -180,6 +178,40 @@ fapi2::ReturnCode post_restore_transition( const fapi2::Target<T>& i_target );
 ///
 fapi2::ReturnCode preload_epow_sequence( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target );
 
+namespace wr_vref
+{
+
+///
+/// @brief Helper to extract the values and ranges from wr_vref_value reg, and
+///        convert JEDEC value to composite
+/// @param[in] i_data - wr vref reg data
+/// @param[out] o_values - vector of composite value
+///
+inline void get_wr_vref_composite_value_helper(const fapi2::buffer<uint64_t> i_data,
+        std::vector<uint64_t>& o_values)
+{
+    FAPI_DBG("get_wr_vref_composite_value_helper() i_data = 0x%016lx", i_data);
+    const std::vector<uint64_t> DRAMS = {0, 1};
+
+    for (const auto l_dram : DRAMS)
+    {
+        uint64_t l_wr_vref_val = 0;
+        bool l_wr_vref_range = 0;
+        uint64_t l_composite_vref = 0;
+
+        mss::dp16::wr_vref::get_wr_vref_value(i_data, l_dram, l_wr_vref_val);
+        mss::dp16::wr_vref::get_wr_vref_range(i_data, l_dram, l_wr_vref_range);
+
+        l_composite_vref = mss::dp16::wr_vref::compute_composite_value(l_wr_vref_range, l_wr_vref_val);
+
+        FAPI_DBG("l_composite_vref: 0x%016lx", l_composite_vref);
+
+        o_values.push_back(l_composite_vref);
+    }
+}
+
+}//ns wr_vref
+
 }//ns nvdimm
 
 }//ns mss
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.C
index 609251cb1..aae4cce28 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2018                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2019                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -38,6 +38,7 @@
 #include <mss.H>
 #include <lib/dimm/mrs_load.H>
 #include <lib/dimm/ddr4/mrs_load_ddr4.H>
+#include <lib/workarounds/ccs_workarounds.H>
 
 using fapi2::TARGET_TYPE_MCBIST;
 using fapi2::TARGET_TYPE_DIMM;
@@ -51,10 +52,12 @@ namespace mss
 ///
 /// @brief Perform the mrs_load operations - TARGET_TYPE_MCA specialization
 /// @param[in] i_target a fapi2::Target<TARGET_TYPE_MCA>
+/// @param[in] i_nvdimm_workaround switch to indicate nvdimm workaround. Default to false
 /// @return FAPI2_RC_SUCCESS if and only if ok
 ///
 template<>
-fapi2::ReturnCode mrs_load<TARGET_TYPE_MCA>( const fapi2::Target<TARGET_TYPE_MCA>& i_target )
+fapi2::ReturnCode mrs_load<TARGET_TYPE_MCA>( const fapi2::Target<TARGET_TYPE_MCA>& i_target,
+        const bool i_nvdimm_workaround )
 {
     const auto& l_mcbist = mss::find_target<TARGET_TYPE_MCBIST>(i_target);
 
@@ -75,7 +78,17 @@ fapi2::ReturnCode mrs_load<TARGET_TYPE_MCA>( const fapi2::Target<TARGET_TYPE_MCA
     // We have to configure the CCS engine to let it know which port these instructions are
     // going out (or whether it's broadcast ...) so lets execute the instructions we presently
     // have so that we kind of do this by port
-    FAPI_TRY( ccs::execute(l_mcbist, l_program, i_target) );
+    // Run the NVDIMM-specific execute procedure if this is for nvdimm workaround.
+    // Otherwise, execute as usual.
+    if (i_nvdimm_workaround)
+    {
+        FAPI_TRY( mss::ccs::workarounds::nvdimm::execute(l_mcbist, l_program, i_target), "Failed ccs execute %s",
+                  mss::c_str(i_target) );
+    }
+    else
+    {
+        FAPI_TRY( mss::ccs::execute(l_mcbist, l_program, i_target), "Failed ccs execute %s", mss::c_str(i_target) );
+    }
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -84,10 +97,12 @@ fapi_try_exit:
 ///
 /// @brief Perform the mrs_load operations - TARGET_TYPE_MCBIST specialization
 /// @param[in] i_target a fapi2::Target<TARGET_TYPE_MCBIST>
+/// @param[in] i_nvdimm_workaround switch to indicate nvdimm workaround. Default to false
 /// @return FAPI2_RC_SUCCESS if and only if ok
 ///
 template<>
-fapi2::ReturnCode mrs_load<TARGET_TYPE_MCBIST>( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target )
+fapi2::ReturnCode mrs_load<TARGET_TYPE_MCBIST>( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target,
+        const bool i_nvdimm_workaround )
 {
     for ( const auto& p : find_targets<TARGET_TYPE_MCA>(i_target) )
     {
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.H
index 2b0418cfb..f19679bc7 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2018                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2019                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -111,10 +111,11 @@ struct mrs_data
 /// @brief Perform the mrs_load operations
 /// @tparam T, the fapi2::TargetType of i_target
 /// @param[in] i_target, a fapi2::Target
+/// @param[in] i_nvdimm_workaround switch to indicate nvdimm workaround. Default to false
 /// @return FAPI2_RC_SUCCESS if and only if ok
 ///
 template< fapi2::TargetType T >
-fapi2::ReturnCode mrs_load( const fapi2::Target<T>& i_target );
+fapi2::ReturnCode mrs_load( const fapi2::Target<T>& i_target, const bool i_nvdimm_workaround = false );
 
 //
 // Implement the polymorphism for mrs_load