Add PHY sequencer refresh settings after draminit

Change-Id: I2fd7738f8909c3567c6cda8640bbe9d70b62bda3
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39757
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39761
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

1 files changed, 28 insertions, 14 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C
index 75d23704d..f8ca39417 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C
@@ -4574,23 +4574,20 @@ fapi_try_exit:
 ///
 fapi2::ReturnCode eff_dimm::cal_step_enable()
 {
-    // Gets the MCS target to use
-    const auto& l_mcs = mss::find_target<TARGET_TYPE_MCS>(iv_dimm);
-
     // These constexpr values are taken from the defiitions in ATTR_MSS_CAL_STEP_ENABLE
     // RD/WR VREF correspond to 0x0400 and 0x0100 respectively.
     constexpr uint64_t ONLY_1D = 0xFAC0;
     constexpr uint64_t RD_VREF_WR_VREF_1D = 0xFFC0;
-    const uint16_t l_cal_step_value = (mss::chip_ec_feature_skip_hw_vref_cal(l_mcs) ? ONLY_1D : RD_VREF_WR_VREF_1D);
+    const uint16_t l_cal_step_value = (mss::chip_ec_feature_skip_hw_vref_cal(iv_mcs) ? ONLY_1D : RD_VREF_WR_VREF_1D);
 
-    FAPI_DBG("%s %s running HW VREF cal. cal_step value: 0x%0x VREF", mss::c_str(l_mcs),
-             mss::chip_ec_feature_skip_hw_vref_cal(l_mcs) ? "not" : "", l_cal_step_value);
+    FAPI_DBG("%s %s running HW VREF cal. cal_step value: 0x%0x VREF", mss::c_str(iv_mcs),
+             mss::chip_ec_feature_skip_hw_vref_cal(iv_mcs) ? "not" : "", l_cal_step_value);
 
     // Sets up the vector
     std::vector<uint16_t> l_cal_step(PORTS_PER_MCS, l_cal_step_value);
 
     // Sets the values
-    return FAPI_ATTR_SET(fapi2::ATTR_MSS_CAL_STEP_ENABLE, l_mcs, UINT16_VECTOR_TO_1D_ARRAY(l_cal_step, PORTS_PER_MCS));
+    return FAPI_ATTR_SET(fapi2::ATTR_MSS_CAL_STEP_ENABLE, iv_mcs, UINT16_VECTOR_TO_1D_ARRAY(l_cal_step, PORTS_PER_MCS));
 }
 
 ///
@@ -4599,22 +4596,39 @@ fapi2::ReturnCode eff_dimm::cal_step_enable()
 ///
 fapi2::ReturnCode eff_dimm::rdvref_enable_bit()
 {
-    // Gets the MCS target to use
-    const auto& l_mcs = mss::find_target<TARGET_TYPE_MCS>(iv_dimm);
-
     // This enables which bits should be run for RD VREF, all 1's indicates that all bits should be run
     constexpr uint64_t DISABLE = 0x0000;
     constexpr uint64_t ENABLE = 0xFFFF;
-    const uint16_t l_vref_enable_value = (mss::chip_ec_feature_skip_hw_vref_cal(l_mcs) ? DISABLE : ENABLE);
+    const uint16_t l_vref_enable_value = (mss::chip_ec_feature_skip_hw_vref_cal(iv_mcs) ? DISABLE : ENABLE);
 
-    FAPI_DBG("%s %s running HW VREF cal. VREF enable value: 0x%0x", mss::c_str(l_mcs),
-             mss::chip_ec_feature_skip_hw_vref_cal(l_mcs) ? "not" : "", l_vref_enable_value);
+    FAPI_DBG("%s %s running HW VREF cal. VREF enable value: 0x%0x", mss::c_str(iv_mcs),
+             mss::chip_ec_feature_skip_hw_vref_cal(iv_mcs) ? "not" : "", l_vref_enable_value);
 
     // Sets up the vector
     std::vector<uint16_t> l_vref_enable(PORTS_PER_MCS, l_vref_enable_value);
 
     // Sets the values
-    return FAPI_ATTR_SET(fapi2::ATTR_MSS_RDVREF_CAL_ENABLE, l_mcs, UINT16_VECTOR_TO_1D_ARRAY(l_vref_enable, PORTS_PER_MCS));
+    return FAPI_ATTR_SET(fapi2::ATTR_MSS_RDVREF_CAL_ENABLE, iv_mcs, UINT16_VECTOR_TO_1D_ARRAY(l_vref_enable,
+                         PORTS_PER_MCS));
+}
+
+///
+/// @brief Determines and sets ATTR_MSS_PHY_SEQ_REFRESH_
+/// @return fapi2::FAPI2_RC_SUCCESS if okay
+///
+fapi2::ReturnCode eff_dimm::phy_seq_refresh()
+{
+    constexpr size_t ENABLE = 1;
+
+    FAPI_DBG("Setting PHY_SEQ_REFRESH to %d on %s", ENABLE, mss::c_str(iv_mcs));
+
+    // Sets up the vector
+    std::vector<uint8_t> l_phy_seq_ref_enable(PORTS_PER_MCS, ENABLE);
+
+    // Sets the values
+    return FAPI_ATTR_SET(fapi2::ATTR_MSS_PHY_SEQ_REFRESH,
+                         iv_mcs,
+                         UINT8_VECTOR_TO_1D_ARRAY(l_phy_seq_ref_enable, PORTS_PER_MCS));
 }
 
 }//mss