Update mss_decode_shadow_regs to use library MRS decoders

Change-Id: I795c57762e2f86390a2bd9c028b62e57450be0f0
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31777
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31908
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

1 files changed, 63 insertions, 20 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C
index a6a0204f8..e71034b4e 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C
@@ -183,39 +183,82 @@ fapi_try_exit:
 }
 
 ///
-/// @brief Given a CCS instruction which contains address bits with an encoded MRS5,
-/// decode and trace the contents
+/// @brief Helper function for mrs05_decode
 /// @param[in] i_inst the CCS instruction
-/// @param[in] i_rank ths rank in question
-/// @return void
+/// @param[in] i_rank the rank in question
+/// @param[out] o_crc_error_clear the crc error clear setting
+/// @param[out] o_ca_parity_error_status the c/a parity error status
+/// @param[out] o_odt_input_buffer the odt input buffer during power down mode setting
+/// @param[out] o_ca_parity the c/a parity persistent error setting
+/// @param[out] o_data_mask the data mask setting
+/// @param[out] o_write_dbi the write dbi setting
+/// @param[out] o_read_dbi the read dbi setting
+/// @param[out] o_ca_parity_latency_buffer the c/a parity latency mode setting
+/// @param[out] o_rtt_park_buffer the rtt_park setting
+/// @return FAPI2_RC_SUCCESS iff ok
 ///
-fapi2::ReturnCode mrs05_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst,
-                               const uint64_t i_rank)
+fapi2::ReturnCode mrs05_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst,
+                                      const uint64_t i_rank,
+                                      uint8_t& o_crc_error_clear,
+                                      uint8_t& o_ca_parity_error_status,
+                                      uint8_t& o_odt_input_buffer,
+                                      uint8_t& o_ca_parity,
+                                      uint8_t& o_data_mask,
+                                      uint8_t& o_write_dbi,
+                                      uint8_t& o_read_dbi,
+                                      fapi2::buffer<uint8_t>& o_ca_parity_latency_buffer,
+                                      fapi2::buffer<uint8_t>& o_rtt_park_buffer)
 {
-    fapi2::buffer<uint8_t> l_ca_parity_latency_buffer;
-    fapi2::buffer<uint8_t> l_rtt_park_buffer;
+    o_ca_parity_latency_buffer = 0;
+    o_rtt_park_buffer = 0;
 
-    mss::swizzle<5, 3, A2>(i_inst.arr0, l_ca_parity_latency_buffer);
-    mss::swizzle<5, 3, A8>(i_inst.arr0, l_rtt_park_buffer);
+    mss::swizzle<5, 3, A2>(i_inst.arr0, o_ca_parity_latency_buffer);
+    mss::swizzle<5, 3, A8>(i_inst.arr0, o_rtt_park_buffer);
 
-    uint8_t l_crc_error_clear = i_inst.arr0.getBit<A3>();
-    uint8_t l_ca_parity_error_status = i_inst.arr0.getBit<A4>();
-    uint8_t l_odt_input_buffer = i_inst.arr0.getBit<A5>();
+    o_crc_error_clear = i_inst.arr0.getBit<A3>();
+    o_ca_parity_error_status = i_inst.arr0.getBit<A4>();
+    o_odt_input_buffer = i_inst.arr0.getBit<A5>();
 
-    uint8_t l_ca_parity = i_inst.arr0.getBit<A9>();
-    uint8_t l_data_mask = i_inst.arr0.getBit<A10>();
-    uint8_t l_write_dbi = i_inst.arr0.getBit<A11>();
-    uint8_t l_read_dbi = i_inst.arr0.getBit<A12>();
+    o_ca_parity = i_inst.arr0.getBit<A9>();
+    o_data_mask = i_inst.arr0.getBit<A10>();
+    o_write_dbi = i_inst.arr0.getBit<A11>();
+    o_read_dbi = i_inst.arr0.getBit<A12>();
 
     FAPI_INF("MR5 rank %d decode: CAPL: 0x%x, CRC_EC: 0x%x, CA_PES: 0x%x, ODT_IB: 0x%x "
              "RTT_PARK: 0x%x, CAP: 0x%x, DM: 0x%x, WDBI: 0x%x, RDBI: 0x%x", i_rank,
-             uint8_t(l_ca_parity_latency_buffer), l_crc_error_clear, l_ca_parity_error_status,
-             l_odt_input_buffer, uint8_t(l_rtt_park_buffer), l_ca_parity, l_data_mask,
-             l_write_dbi, l_read_dbi);
+             uint8_t(o_ca_parity_latency_buffer), o_crc_error_clear, o_ca_parity_error_status,
+             o_odt_input_buffer, uint8_t(o_rtt_park_buffer), o_ca_parity, o_data_mask,
+             o_write_dbi, o_read_dbi);
 
     return FAPI2_RC_SUCCESS;
 }
 
+///
+/// @brief Given a CCS instruction which contains address bits with an encoded MRS5,
+/// decode and trace the contents
+/// @param[in] i_inst the CCS instruction
+/// @param[in] i_rank ths rank in question
+/// @return FAPI2_RC_SUCCESS iff ok
+///
+fapi2::ReturnCode mrs05_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst,
+                               const uint64_t i_rank)
+{
+    fapi2::buffer<uint8_t> l_ca_parity_latency_buffer;
+    fapi2::buffer<uint8_t> l_rtt_park_buffer;
+
+    uint8_t l_crc_error_clear = 0;
+    uint8_t l_ca_parity_error_status = 0;
+    uint8_t l_odt_input_buffer = 0;
+    uint8_t l_ca_parity = 0;
+    uint8_t l_data_mask = 0;
+    uint8_t l_write_dbi = 0;
+    uint8_t l_read_dbi = 0;
+
+    return mrs05_decode_helper(i_inst, i_rank, l_crc_error_clear, l_ca_parity_error_status,
+                               l_odt_input_buffer, l_ca_parity, l_data_mask, l_write_dbi,
+                               l_read_dbi, l_ca_parity_latency_buffer, l_rtt_park_buffer);
+}
+
 fapi2::ReturnCode (*mrs05_data::make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         const mrs05_data& i_data,
         ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst,