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| author | Stephen Glancy <sglancy@us.ibm.com> | 2016-08-16 10:35:34 -0500 |
|---|---|---|
| committer | Stephen M. Cprek <smcprek@us.ibm.com> | 2016-08-17 17:34:29 -0400 |
| commit | dbf7a3f38b467b73e39c9fc2ceb6121e95c5b020 (patch) | |
| tree | 6566a8ccacead6d16f81c5f612c0d48031097c41 /src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C | |
| parent | ad21256bb30d7281f6a57f541226c546735088ab (diff) | |
| download | talos-hostboot-dbf7a3f38b467b73e39c9fc2ceb6121e95c5b020.tar.gz talos-hostboot-dbf7a3f38b467b73e39c9fc2ceb6121e95c5b020.zip | |
Updated MR3 attributes in effective config
Removed the following attributes:
mpr page
mpr mode
per-dram addressability
temperature sensor readout
mpr read format
Updated the following attribute in effective config:
wr cmd latency
Change-Id: I8d417700ed1d89e0205de61051a42f6e435da082
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28335
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28339
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Stephen M. Cprek <smcprek@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C index ae6277d1c..45ba9e8dd 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C @@ -55,14 +55,14 @@ namespace ddr4 /// @param[out] fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok /// mrs03_data::mrs03_data( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, fapi2::ReturnCode& o_rc ): - iv_mpr_mode(0), - iv_mpr_page(0), + iv_mpr_mode(fapi2::ENUM_ATTR_EFF_MPR_MODE_DISABLE), + iv_mpr_page(fapi2::ENUM_ATTR_EFF_MPR_PAGE_PG0), iv_geardown(0), - iv_pda(0), + iv_pda(fapi2::ENUM_ATTR_EFF_PER_DRAM_ACCESS_DISABLE), iv_crc_wr_latency(0), - iv_temp_readout(0), + iv_temp_readout(fapi2::ENUM_ATTR_EFF_TEMP_READOUT_DISABLE), iv_fine_refresh(0), - iv_read_format(0) + iv_read_format(fapi2::ENUM_ATTR_EFF_MPR_RD_FORMAT_SERIAL) { FAPI_TRY( mss::eff_mpr_mode(i_target, iv_mpr_mode) ); FAPI_TRY( mss::eff_mpr_page(i_target, iv_mpr_page) ); @@ -123,7 +123,7 @@ fapi2::ReturnCode mrs03(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, constexpr uint64_t LOWEST_WL = 4; constexpr uint64_t WL_COUNT = 3; // 4 5 6 - constexpr uint8_t crc_wr_latency_map[WL_COUNT] = { 1, 2, 3 }; + constexpr uint8_t crc_wr_latency_map[WL_COUNT] = { 0, 1, 2 }; fapi2::buffer<uint8_t> l_crc_wr_latency_buffer; |
