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| author | Stephen Glancy <sglancy@us.ibm.com> | 2016-10-11 20:54:09 -0500 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2016-10-31 10:36:30 -0400 |
| commit | c7cf0b2d56200537be4227b246fa5c4754cc7306 (patch) | |
| tree | 1d00ece50c9f5a6e582e431ebc2e1b174edbb319 /src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C | |
| parent | a0575efc0dae3b41ee95e55d5a5e7acb12418c90 (diff) | |
| download | talos-hostboot-c7cf0b2d56200537be4227b246fa5c4754cc7306.tar.gz talos-hostboot-c7cf0b2d56200537be4227b246fa5c4754cc7306.zip | |
Fixed CL and timing bugs, unit test augmentations
Fix 3DS timing params for SLR and DLR and add unit tests.
Fix CL setting for non-configured ports and add unit CL tests
Fixed SPD timing errors, CL, MR, and ddr_phy UT bugs
Change-Id: Icc7efcc6f5a01ceee168a10ca8236cb656ba013c
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31066
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31484
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C index 71a51e7bb..9f2aafc01 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C @@ -122,7 +122,7 @@ fapi2::ReturnCode mrs00(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, constexpr uint8_t wr_map[WR_COUNT] = { // 10 12 14 16 18 20 22 24 26 - 0b0000, 0, 0b0001, 0, 0b0001, 0, 0b0011, 0, 0b0100, 0, 0b0101, 0, 0b0111, 0, 0b0110, 0, 0b1000 + 0b0000, 0, 0b0001, 0, 0b0010, 0, 0b0011, 0, 0b0100, 0, 0b0101, 0, 0b0111, 0, 0b0110, 0, 0b1000 }; // Map from the CAS Latency attribute to the bits in the MRS @@ -241,4 +241,3 @@ fapi2::ReturnCode (*mrs00_data::decode)(const ccs::instruction_t<fapi2::TARGET_T } // ns ddr4 } // ns mss - |
