STOP Recovery: Misc infra. updates to enable PM FFDC in HOMER

1. Updated STOP Recovery wrapper for test
2. Enable GPE0/1, shared region sram data collection
3. FIR and OCC register collection support
4. PM FFDC Section Header and Region Inits
5. Defined constants for FFDC region boundary in HOMER
6. Fixed miscellaneous review comments and UT bugs

Change-Id: I802e6ddb919efaa09b9ffab5ddd3283d8efa9323
RTC: 179599
CQ: SW406487
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48987
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48992
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

2 files changed, 96 insertions, 25 deletions

diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
index 6d24ec593..876f8a168 100644
--- a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
@@ -274,6 +274,13 @@ HCD_CONST(QUAD_SCOM_RESTORE_SIZE_PER_QUAD,
           (SCOM_RESTORE_ENTRY_SIZE* QUAD_SCOM_RESTORE_REGS_PER_QUAD))
 
 HCD_CONST(QUAD_SCOM_RESTORE_SIZE_TOTAL,         (6 * ONE_KB)) //rounded to 6KB
+//FFDC Region
+HCD_CONST(FFDC_REGION_QPMR_BASE_OFFSET, 0xE0000)    //Offset wrt to QPMR base
+HCD_CONST(FFDC_REGION_SIZE,  (80 * ONE_KB))
+//end offset of FFDC region wrt to QPMR base
+HCD_CONST(FFDC_REGION_QPMR_END_OFFSET, (FFDC_REGION_QPMR_BASE_OFFSET +
+                                        FFDC_REGION_SIZE ))
+//---------------------------------------------------------------------------------------
 
 //---------------------------------------------------------------------------------------
 
@@ -540,7 +547,8 @@ HCD_CONST(WOF_TABLE_RESERVE,
 HCD_CONST(PGPE_IMAGE_RESERVE_SIZE,
           (OCC_PSTATE_PARAM_BLOCK_PPMR_OFFSET - PGPE_IMAGE_PPMR_OFFSET - PGPE_IMAGE_SIZE - PGPE_AUX_TASK_SIZE))
 
-//FFDC Magic Words
+// PM FFDC Magic Words
+HCD_CONST(FFDC_MAGIC_NUM,             (0x46464443)) //"FFDC"
 HCD_CONST(FFDC_CME_MAGIC_NUM,         (0x434d455f)) //"CME_"
 HCD_CONST(FFDC_SGPE_MAGIC_NUM,        (0x53475045)) //"SGPE"
 HCD_CONST(FFDC_PGPE_MAGIC_NUM,        (0x50475045)) //"PGPE"
@@ -548,33 +556,90 @@ HCD_CONST(FFDC_OCC_MAGIC_NUM,         (0x4f43435f)) //"OCC_"
 HCD_CONST(FFDC_CPPM_MAGIC_NUM,        (0x4350504d)) //"CPPM"
 HCD_CONST(FFDC_QPPM_MAGIC_NUM,        (0x5150504d)) //"QPPM"
 HCD_CONST(FFDC_QUAD_MAGIC_NUM,        (0x51554144)) //"QUAD"
+HCD_CONST(FFDC_FIR_MAGIC_NUM,         (0x46495200)) //"FIR"
+
+// PM FFDC Region Layout Sizes
+HCD_CONST(FFDC_SCOM_REG_ID_VAL_SIZE,    12)
+
+// PPE FFDC Section
+// section common to SGPE and PGPE FFDC
 
-//FFDC Region Layout
+// 27 CME internal regs, 10 CME regs, 1 buffer/pad
+HCD_CONST(FFDC_PPE_INTL_REGISTERS_MAX,  38)
+
+HCD_CONST(FFDC_PPE_HDR_SIZE ,           0x18)
 HCD_CONST(FFDC_PPE_SCORE_BOARD_SIZE,    0x200)
 HCD_CONST(FFDC_PPE_IMG_HDR_SIZE,        0x80)
 HCD_CONST(FFDC_PPE_XIR_SIZE,            0x28)
 HCD_CONST(FFDC_PPE_SPR_SIZE,            0x80)
 HCD_CONST(FFDC_PPE_GPR_SIZE,            0x80)
-HCD_CONST(FFDC_PPE_INTERNAL_REG_SIZE,   0x78)
+HCD_CONST(FFDC_PPE_INTERNAL_REG_SIZE,   (FFDC_PPE_INTL_REGISTERS_MAX*
+          FFDC_SCOM_REG_ID_VAL_SIZE))
 HCD_CONST(FFDC_PPE_TRACES_SIZE,         0x200)
-HCD_CONST(FFDC_PPE_HDR_SIZE ,           0x18)
-HCD_CONST(FFDC_QUAD_HDR_SIZE ,          0x18)
-HCD_CONST(FFDC_CPPM_REGISTERS_SIZE,     0x160)
-HCD_CONST(FFDC_PPE_BLOCK_SIZE,          0x6FC)
-HCD_CONST(FFDC_QPPM_REGISTERS_SIZE,     0x154)
-HCD_CONST(FFDC_HOMER_TOP_HEADER ,       0x38)
-HCD_CONST(FFDC_QUAD_REGION_SIZE,        0x14DC)
+HCD_CONST(FFDC_PPE_BLOCK_SIZE,          (FFDC_PPE_HDR_SIZE +
+          FFDC_PPE_SCORE_BOARD_SIZE +
+          FFDC_PPE_IMG_HDR_SIZE +
+          FFDC_PPE_XIR_SIZE +
+          FFDC_PPE_SPR_SIZE +
+          FFDC_PPE_GPR_SIZE +
+          FFDC_PPE_INTERNAL_REG_SIZE +
+          FFDC_PPE_TRACES_SIZE ))
+
+// FIR FFDC Section
+HCD_CONST(FFDC_PM_CME_FIR_REGISTERS_MAX, 1)
+HCD_CONST(FFDC_PM_FIR_REGISTERS_MAX,     2)
+
+HCD_CONST(FFDC_FIR_HDR_SIZE ,           0x10)
+HCD_CONST(FFDC_CME_FIR_REGISTERS_SIZE,  (FFDC_PM_CME_FIR_REGISTERS_MAX*
+          FFDC_SCOM_REG_ID_VAL_SIZE))
+HCD_CONST(FFDC_FIR_REGISTER_SIZE,       (FFDC_PM_FIR_REGISTERS_MAX*
+          FFDC_SCOM_REG_ID_VAL_SIZE))
+HCD_CONST(FFDC_FIR_REGION_SIZE,         (FFDC_FIR_HDR_SIZE +
+          (FFDC_CME_FIR_REGISTERS_SIZE* MAX_CMES_PER_CHIP) +
+          FFDC_FIR_REGISTER_SIZE ))
+
+// PPM FFDC Sections
+HCD_CONST(FFDC_PPM_HDR_SIZE,            0x10)
+
+// Core PPM
+HCD_CONST(FFDC_CPPM_REGISTERS_MAX,      28)
+HCD_CONST(FFDC_CPPM_REGISTERS_SIZE,     (FFDC_CPPM_REGISTERS_MAX*
+          FFDC_SCOM_REG_ID_VAL_SIZE))
+HCD_CONST(FFDC_CPPM_REGION_SIZE,        (FFDC_PPM_HDR_SIZE +
+          FFDC_CPPM_REGISTERS_SIZE))
+
+// Quad PPM
+HCD_CONST(FFDC_QPPM_REGISTERS_MAX,      28) // 1 extra for pad
+HCD_CONST(FFDC_QPPM_REGISTERS_SIZE,     (FFDC_QPPM_REGISTERS_MAX*
+          FFDC_SCOM_REG_ID_VAL_SIZE))
+HCD_CONST(FFDC_QPPM_REGION_SIZE,        (FFDC_PPM_HDR_SIZE +
+          FFDC_QPPM_REGISTERS_SIZE))
+
+// Quad FFDC Section
+HCD_CONST(FFDC_QUAD_HDR_SIZE ,          0x20)
+HCD_CONST(FFDC_QUAD_REGION_SIZE,        (FFDC_QUAD_HDR_SIZE +
+          (FFDC_CPPM_REGION_SIZE* MAX_CORES_PER_QUAD) +
+          (FFDC_PPE_BLOCK_SIZE* MAX_CMES_PER_QUAD) +
+          FFDC_QPPM_REGION_SIZE))
+
+// SGPE FFDC Section
 HCD_CONST(FFDC_SGPE_REGION_SIZE,        (FFDC_PPE_BLOCK_SIZE))
+// PGPE FFDC Section
 HCD_CONST(FFDC_PGPE_REGION_SIZE,        (FFDC_PPE_BLOCK_SIZE))
-HCD_CONST(FFDC_OCC_REGION_HDR_SIZE,     0x18)
+
+// OCC FFDC Section
+HCD_CONST(FFDC_OCC_REGISTERS_MAX,       202) // 1 extra for pad
+
+HCD_CONST(FFDC_OCC_REGION_HDR_SIZE,     0x20)
 HCD_CONST(FFDC_TRACE_ERR_SIZE,          (8 * ONE_KB))
-HCD_CONST(FFDC_TRACE_IMP_SIZE,          (FFDC_TRACE_ERR_SIZE))
-HCD_CONST(FFDC_TRACE_INF_SIZE,          (FFDC_TRACE_ERR_SIZE))
-HCD_CONST(FFDC_TRACE_SSX_SIZE ,         (FFDC_TRACE_ERR_SIZE))
+HCD_CONST(FFDC_TRACE_IMP_SIZE,          (8 * ONE_KB))
+HCD_CONST(FFDC_TRACE_INF_SIZE,          (8 * ONE_KB))
+HCD_CONST(FFDC_TRACE_SSX_SIZE ,         (8 * ONE_KB))
 HCD_CONST(FFDC_TRACE_GPE0_SIZE,         0x200)
 HCD_CONST(FFDC_TRACE_GPE1_SIZE,         0x200)
 HCD_CONST(FFDC_SHARED_SRAM_SIZE,        0x200)
-HCD_CONST(FFDC_OCC_REGS_SIZE,           0x580)
+HCD_CONST(FFDC_OCC_REGS_SIZE,           (FFDC_OCC_REGISTERS_MAX*
+          FFDC_SCOM_REG_ID_VAL_SIZE))
 HCD_CONST(FFDC_OCC_REGION_SIZE,         (FFDC_OCC_REGION_HDR_SIZE +
           FFDC_TRACE_ERR_SIZE +
           FFDC_TRACE_IMP_SIZE +
@@ -584,8 +649,17 @@ HCD_CONST(FFDC_OCC_REGION_SIZE,         (FFDC_OCC_REGION_HDR_SIZE +
           FFDC_TRACE_GPE1_SIZE +
           FFDC_SHARED_SRAM_SIZE +
           FFDC_OCC_REGS_SIZE))
-HCD_CONST(FFDC_REGION_QPMR_BASE_OFFSET, 0xE0000)
+
+// Overall PM FFDC Section
+HCD_CONST(FFDC_PM_HEADER_SIZE,          0x38)
+HCD_CONST(FFDC_PM_REGION_SIZE,          (FFDC_PM_HEADER_SIZE +
+          FFDC_FIR_REGION_SIZE +
+          (FFDC_QUAD_REGION_SIZE * 6) +
+          FFDC_SGPE_REGION_SIZE +
+          FFDC_PGPE_REGION_SIZE +
+          FFDC_OCC_REGION_SIZE))
+
 HCD_CONST(FFDC_REGION_HOMER_BASE_OFFSET,
-          (QPMR_HOMER_OFFSET + FFDC_REGION_QPMR_BASE_OFFSET))
+          (FFDC_REGION_QPMR_BASE_OFFSET + QPMR_HOMER_OFFSET))
 
 #endif /* __HCD_MEMMAP_BASE_H__ */
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H
index 4e5fcb4bb..ede7ce4a7 100644
--- a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H
@@ -51,23 +51,20 @@ HCD_CONST(OCC_SRAM_BASE_ADDR,                   0xFFF00000)
 HCD_CONST(GPE0_SRAM_BASE_ADDR,                  0xFFF01000)
 HCD_CONST(GPE1_SRAM_BASE_ADDR,                  0xFFF10000)
 
-/// Base Addresses for various traces regions in OCC SRAM
-HCD_CONST(OCC_SRAM_TRACE_BUF_BASE_SSX_PTR,      0xFFF40824)
+/// Base Addresses for various debug/trace regions in OCC SRAM
 HCD_CONST(OCC_SRAM_TRACE_BUF_BASE_ERR,          0xFFFB4000)
 HCD_CONST(OCC_SRAM_TRACE_BUF_BASE_INF,          0xFFFB6000)
 HCD_CONST(OCC_SRAM_TRACE_BUF_BASE_IMP,          0xFFFB8000)
-// @TODO: HCD_CONST(OCC_SRAM_TRACE_BUF_BASE_SHARED,    0x0)
-HCD_CONST(GPE0_SRAM_TRACE_BUF_PTR,              GPE0_SRAM_BASE_ADDR + 0x184)
-HCD_CONST(GPE1_SRAM_TRACE_BUF_PTR,              GPE1_SRAM_BASE_ADDR + 0x184)
+HCD_CONST(OCC_SRAM_TRACE_BUF_BASE_SSX_PTR,      0xFFF40824)
+
+// Offset to trace buf ptr and trace buffer size from base
+HCD_CONST(GPE_DEBUG_PTR_OFFSET,                      0x180)
 
 // Size of various traces regions in OCC SRAM
 HCD_CONST(OCC_SRAM_TRACE_BUF_SSX_SIZE_PTR,      0xFFF40828)
 HCD_CONST(OCC_SRAM_TRACE_BUF_ERR_SIZE,          (8 * ONE_KB))
 HCD_CONST(OCC_SRAM_TRACE_BUF_INF_SIZE,          (8 * ONE_KB))
 HCD_CONST(OCC_SRAM_TRACE_BUF_IMP_SIZE,          (8 * ONE_KB))
-// @TODO: HCD_CONST(OCC_SRAM_TRACE_BUF_SHARED_SIZE, )
-HCD_CONST(GPE0_SRAM_TRACE_BUF_SIZE_PTR,         (GPE0_SRAM_BASE_ADDR + 0x188))
-HCD_CONST(GPE1_SRAM_TRACE_BUF_SIZE_PTR,         (GPE1_SRAM_BASE_ADDR + 0x188))
 
 HCD_CONST(OCC_SRAM_IPC_REGION_SIZE,             (4 * ONE_KB))
 HCD_CONST(OCC_SRAM_GPE0_REGION_SIZE,            (60 * ONE_KB))